diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-12-11 21:38:43 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-12-11 21:38:43 +0000 |
| commit | 3e268cc0dd570bb2283652669024afec643fbb3c (patch) | |
| tree | 130617f8ea322b9c62eb4d8f6191514cf051a788 /llvm/test/CodeGen/AMDGPU | |
| parent | c40c5e520b59185e1ec3217713596c9a950cde9b (diff) | |
| download | bcm5719-llvm-3e268cc0dd570bb2283652669024afec643fbb3c.tar.gz bcm5719-llvm-3e268cc0dd570bb2283652669024afec643fbb3c.zip | |
LSR: Check more intrinsic pointer operands
llvm-svn: 320424
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll index 36eade395b7..75ce7f54ae3 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll @@ -407,6 +407,19 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64 addrspace ret void } +; GCN-LABEL: {{^}}nocse_lds_atomic_inc_ret_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] +; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] +define amdgpu_kernel void @nocse_lds_atomic_inc_ret_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(3)* %ptr) #0 { + %result0 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 false) + %result1 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 false) + + store i32 %result0, i32 addrspace(1)* %out0 + store i32 %result1, i32 addrspace(1)* %out1 + ret void +} + attributes #0 = { nounwind } attributes #1 = { nounwind readnone } attributes #2 = { nounwind argmemonly } |
