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| author | Tom Stellard <tstellar@redhat.com> | 2018-07-13 21:05:14 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2018-07-13 21:05:14 +0000 |
| commit | 390a5f47740d2ff1515abb92c6f85f5441989197 (patch) | |
| tree | b8b5c5234715310487b3ee0bd63b52d2bad55fb5 /llvm/test/CodeGen/AMDGPU | |
| parent | f0831eef0b35e5296a1741078f1bebc255a7ff25 (diff) | |
| download | bcm5719-llvm-390a5f47740d2ff1515abb92c6f85f5441989197.tar.gz bcm5719-llvm-390a5f47740d2ff1515abb92c6f85f5441989197.zip | |
AMDGPU/GlobalISel: Implement select() for @llvm.amdgcn.exp
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45882
llvm-svn: 337046
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir new file mode 100644 index 00000000000..071625f98c0 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir @@ -0,0 +1,33 @@ +# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s + +--- +name: exp0 +legalized: true +regBankSelected: true + +# CHECK: name: exp0 +body: | + bb.0: + liveins: $vgpr0 + %0:vgpr(s32) = COPY $vgpr0 + %1:sgpr(s32) = G_CONSTANT i32 1 + %2:sgpr(s32) = G_CONSTANT i32 15 + %3:sgpr(s1) = G_CONSTANT i1 0 + %4:sgpr(s1) = G_CONSTANT i1 1 + + ; CHECK: EXP 1, %0, %0, %0, %0, 0, 0, 15, implicit $exec + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %1:sgpr(s32), %2:sgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %3:sgpr(s1), %3:sgpr(s1) + + ; CHECK: EXP_DONE 1, %0, %0, %0, %0, 0, 0, 15, implicit $exec + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %1:sgpr(s32), %2:sgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %4:sgpr(s1), %3:sgpr(s1) + + %5:vgpr(<2 x s16>) = G_BITCAST %0(s32) + + ; CHECK: [[UNDEF0:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK: EXP 1, %0, %0, [[UNDEF0]], [[UNDEF0]], 0, 1, 15, implicit $exec + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), %1:sgpr(s32), %2:sgpr(s32), %5:vgpr(<2 x s16>), %5:vgpr(<2 x s16>), %3:sgpr(s1), %3:sgpr(s1) + + ; CHECK: [[UNDEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; CHECK: EXP_DONE 1, %0, %0, [[UNDEF1]], [[UNDEF1]], 0, 1, 15, implicit $exec + G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), %1:sgpr(s32), %2:sgpr(s32), %5:vgpr(<2 x s16>), %5:vgpr(<2 x s16>), %4:sgpr(s1), %3:sgpr(s1) + |
