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| author | Philip Reames <listmail@philipreames.com> | 2017-12-31 03:34:36 +0000 |
|---|---|---|
| committer | Philip Reames <listmail@philipreames.com> | 2017-12-31 03:34:36 +0000 |
| commit | 232951dfb21442e6da8ecbf115808314bd2d2404 (patch) | |
| tree | da14e6727139b4066a32c488ac2057684980e15c /llvm/test/CodeGen/AMDGPU | |
| parent | 7db85c52826bed276d5f1694744d3982588394b3 (diff) | |
| download | bcm5719-llvm-232951dfb21442e6da8ecbf115808314bd2d2404.tar.gz bcm5719-llvm-232951dfb21442e6da8ecbf115808314bd2d2404.zip | |
2nd attempt at "fixing" amdgpu tests after r321575
The test needs to be changed; it was exercising UB and that likely wasn't the intent of the test author. I simply removed the checks because I have absolutely no idea what this test was trying to accomplish. With multiple check patterns, no explanation, and no familiarity on my part with the ISA a true fix is going to have to come from someone familiar with the target.
llvm-svn: 321591
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll index d05ad7c6ec1..5218c784586 100644 --- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll +++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll @@ -470,32 +470,6 @@ bb2: ; GCN-LABEL: {{^}}insert_adjacent_blocks: -; GCN: s_load_dword [[ARG:s[0-9]+]] -; GCN: s_cmp_lg_u32 -; GCN: s_cbranch_scc0 [[BB4:BB[0-9]+_[0-9]+]] - -; GCN: buffer_load_dwordx4 -; MOVREL: s_mov_b32 m0, -; MOVREL: v_movreld_b32_e32 - -; IDXMODE: s_set_gpr_idx_on s{{[0-9]+}}, dst -; IDXMODE: v_mov_b32_e32 -; IDXMODE: s_set_gpr_idx_off - -; GCN: s_branch [[ENDBB:BB[0-9]+_[0-9]+]] - -; GCN: [[BB4]]: -; GCN: buffer_load_dwordx4 -; MOVREL: s_mov_b32 m0, -; MOVREL: v_movreld_b32_e32 - -; IDXMODE: s_set_gpr_idx_on s{{[0-9]+}}, dst -; IDXMODE: v_mov_b32_e32 -; IDXMODE: s_set_gpr_idx_off - -; GCN: [[ENDBB]]: -; GCN: buffer_store_dword -; GCN: s_endpgm define amdgpu_kernel void @insert_adjacent_blocks(i32 %arg, float %val0) #0 { bb: %tmp = icmp eq i32 %arg, 0 |
