GlobalISel: Enforce operand types for constants

A number of of tests were using imm operands, not cimm. Since CSE
relies on the exact ConstantInt* pointer used, and implicit
conversions are generally evil, also enforce the bitsize of the types.

llvm-svn: 353113

13 files changed, 47 insertions, 46 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
index d6ead4ba808..b7af7a91971 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
@@ -45,7 +45,7 @@ regBankSelected: true
 body: |
   bb.0:
     %0:vgpr(p0) = G_IMPLICIT_DEF
-    %1:vgpr(s32) = G_CONSTANT 4
+    %1:vgpr(s32) = G_CONSTANT i32 4
     G_STORE %1, %0 :: (store 4)
 ...
 
@@ -62,7 +62,7 @@ body: |
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
     ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr
     %0:vgpr(p1) = G_IMPLICIT_DEF
-    %1:vgpr(s32) = G_CONSTANT 4
+    %1:vgpr(s32) = G_CONSTANT i32 4
     G_STORE %1, %0 :: (store 4, addrspace 1)
 ...
 ---
@@ -78,7 +78,7 @@ body: |
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
     ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr
     %0:vgpr(p3) = G_IMPLICIT_DEF
-    %1:vgpr(s32) = G_CONSTANT 4
+    %1:vgpr(s32) = G_CONSTANT i32 4
     G_STORE %1, %0 :: (store 4, addrspace 1)
 ...
 ---
@@ -94,6 +94,6 @@ body: |
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
     ; GCN: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, 0, implicit $exec, implicit $flat_scr
     %0:vgpr(p4) = G_IMPLICIT_DEF
-    %1:vgpr(s32) = G_CONSTANT 4
+    %1:vgpr(s32) = G_CONSTANT i32 4
     G_STORE %1, %0 :: (store 4, addrspace 1)
 ...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
index 7f6bf22a83b..2267795bae9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
@@ -31,7 +31,7 @@ body: |
     ; CHECK: S_NOP 0, implicit [[AND]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
-    %2:_(s32) = G_CONSTANT i64 0
+    %2:_(s32) = G_CONSTANT i32 0
     %3:_(s1) = G_ICMP intpred(ne), %0, %2
     %4:_(s1) = G_ICMP intpred(ne), %1, %2
     %5:_(s32) = G_AND %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
index df4680d9147..d187aeafbca 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
@@ -253,7 +253,7 @@ body: |
 
     ; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i1
     ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s1>) = G_IMPLICIT_DEF
-    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i32 0
+    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
     ; CHECK: [[UV:%[0-9]+]]:_(s1), [[UV1:%[0-9]+]]:_(s1) = G_UNMERGE_VALUES [[DEF]](<2 x s1>)
     ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[UV]](s1)
     ; CHECK: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[UV1]](s1)
@@ -263,7 +263,7 @@ body: |
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
     ; CHECK: $vgpr0 = COPY [[COPY]](s32)
     %0:_(<2 x s1>) = G_IMPLICIT_DEF
-    %1:_(s1) = G_CONSTANT i32 0
+    %1:_(s1) = G_CONSTANT i1 false
     %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
     %3:_(s32) = G_ANYEXT %2
     $vgpr0 = COPY %3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
index 302e1bfaaf2..ca6bbea9095 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
@@ -88,7 +88,7 @@ body: |
     ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
     ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
     ; CHECK: $vgpr0 = COPY [[COPY5]](s32)
-    %0:_(s8) = G_CONSTANT i16 0
+    %0:_(s8) = G_CONSTANT i8 0
     %1:_(s32) = COPY $vgpr0
     %2:_(s8) = G_TRUNC %1
     %3:_(s1) = G_ICMP intpred(ne), %0, %2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
index 72f6eca353f..53a56dcaf9f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
@@ -31,7 +31,7 @@ body: |
     ; CHECK: S_NOP 0, implicit [[OR]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
-    %2:_(s32) = G_CONSTANT i64 0
+    %2:_(s32) = G_CONSTANT i32 0
     %3:_(s1) = G_ICMP intpred(ne), %0, %2
     %4:_(s1) = G_ICMP intpred(ne), %1, %2
     %5:_(s32) = G_OR %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
index a794123a020..81c0556ba5c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
@@ -97,8 +97,8 @@ body: |
     %1:_(s32) = COPY $vgpr0
 
     %2:_(s1) = G_ICMP intpred(ne), %0, %1
-    %3:_(s8) = G_CONSTANT i16 1
-    %4:_(s8) = G_CONSTANT i16 2
+    %3:_(s8) = G_CONSTANT i8 1
+    %4:_(s8) = G_CONSTANT i8 2
     %5:_(s8) = G_SELECT %2, %3, %4
     %6:_(s32) = G_ANYEXT %5
     $vgpr0 = COPY %6
@@ -125,8 +125,8 @@ body: |
     %1:_(s32) = COPY $vgpr0
 
     %2:_(s1) = G_ICMP intpred(ne), %0, %1
-    %3:_(s7) = G_CONSTANT i16 1
-    %4:_(s7) = G_CONSTANT i16 2
+    %3:_(s7) = G_CONSTANT i7 1
+    %4:_(s7) = G_CONSTANT i7 2
     %5:_(s7) = G_SELECT %2, %3, %4
     %6:_(s32) = G_ANYEXT %5
     $vgpr0 = COPY %6
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
index 566bdefeb80..706adbfc9ac 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
@@ -31,7 +31,7 @@ body: |
     ; CHECK: S_NOP 0, implicit [[XOR]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $vgpr1
-    %2:_(s32) = G_CONSTANT i64 0
+    %2:_(s32) = G_CONSTANT i32 0
     %3:_(s1) = G_ICMP intpred(ne), %0, %2
     %4:_(s1) = G_ICMP intpred(ne), %1, %2
     %5:_(s32) = G_XOR %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
index e53b05b6eeb..9e2d6626985 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
@@ -77,7 +77,7 @@ body: |
     ; CHECK-LABEL: name: and_i1_scc_scc
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
     ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
@@ -86,7 +86,7 @@ body: |
     ; CHECK: S_NOP 0, implicit [[AND]](s1)
       %0:_(s32) = COPY $sgpr0
       %1:_(s32) = COPY $sgpr1
-      %2:_(s32) = G_CONSTANT i64 0
+      %2:_(s32) = G_CONSTANT i32 0
       %4:_(s1) = G_ICMP intpred(ne), %0, %2
       %5:_(s1) = G_ICMP intpred(ne), %1, %2
       %6:_(s1) = G_AND %4, %5
@@ -103,7 +103,7 @@ body: |
     ; CHECK-LABEL: name: and_i1_vcc_vcc
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
     ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
@@ -112,7 +112,7 @@ body: |
     ; CHECK: S_NOP 0, implicit [[AND]](s1)
       %0:_(s32) = COPY $vgpr0
       %1:_(s32) = COPY $vgpr1
-      %2:_(s32) = G_CONSTANT i64 0
+      %2:_(s32) = G_CONSTANT i32 0
       %4:_(s1) = G_ICMP intpred(ne), %0, %2
       %5:_(s1) = G_ICMP intpred(ne), %1, %2
       %6:_(s1) = G_AND %4, %5
@@ -129,7 +129,7 @@ body: |
     ; CHECK-LABEL: name: and_i1_scc_vcc
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
     ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
     ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
@@ -138,7 +138,7 @@ body: |
     ; CHECK: S_NOP 0, implicit [[AND]](s1)
       %0:_(s32) = COPY $sgpr0
       %1:_(s32) = COPY $vgpr0
-      %2:_(s32) = G_CONSTANT i64 0
+      %2:_(s32) = G_CONSTANT i32 0
       %4:_(s1) = G_ICMP intpred(ne), %0, %2
       %5:_(s1) = G_ICMP intpred(ne), %1, %2
       %6:_(s1) = G_AND %4, %5
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
index 2370f5b96a5..dad757b41f1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir
@@ -27,8 +27,9 @@ legalized:       true
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_fconstant_f16_1
-    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT half 0xH3C00
-    %0:_(s32) = G_FCONSTANT half 1.0
+    ; CHECK: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH3C00
+    %0:_(s16) = G_FCONSTANT half 1.0
+    %1:_(s32) = G_ANYEXT %0
 ...
 
 ---
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
index 72fed92e9d0..929882ac679 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
@@ -13,20 +13,20 @@ body: |
     ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[ICMP]]
     ; GREEDY-LABEL: name: sadde_s32_sss
     ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[SADDE:%[0-9]+]]:sgpr(s32), [[SADDE1:%[0-9]+]]:scc(s1) = G_SADDE [[COPY]], [[COPY1]], [[ICMP]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s32) = COPY $sgpr2
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_SADDE %0, %1, %4
 ...
@@ -42,7 +42,7 @@ body: |
     ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
@@ -51,7 +51,7 @@ body: |
     ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
@@ -59,7 +59,7 @@ body: |
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $sgpr0
     %2:_(s32) = COPY $sgpr1
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_SADDE %0, %1, %4
 ...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
index 7de8f9eb951..ca360cdd376 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
@@ -13,20 +13,20 @@ body: |
     ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
     ; GREEDY-LABEL: name: ssube_s32_sss
     ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[SSUBE:%[0-9]+]]:sgpr(s32), [[SSUBE1:%[0-9]+]]:scc(s1) = G_SSUBE [[COPY]], [[COPY1]], [[ICMP]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s32) = COPY $sgpr2
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_SSUBE %0, %1, %4
 ...
@@ -42,7 +42,7 @@ body: |
     ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
@@ -51,7 +51,7 @@ body: |
     ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
@@ -59,7 +59,7 @@ body: |
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $sgpr0
     %2:_(s32) = COPY $sgpr1
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_SSUBE %0, %1, %4
 ...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
index 83b4513eb23..2477ea07607 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
@@ -12,20 +12,20 @@ body: |
     ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[ICMP]]
     ; GREEDY-LABEL: name: uadde_s32_sss
     ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:scc(s1) = G_UADDE [[COPY]], [[COPY1]], [[ICMP]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s32) = COPY $sgpr2
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_UADDE %0, %1, %4
 ...
@@ -41,7 +41,7 @@ body: |
     ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
@@ -50,7 +50,7 @@ body: |
     ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
@@ -58,7 +58,7 @@ body: |
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $sgpr0
     %2:_(s32) = COPY $sgpr1
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_UADDE %0, %1, %4
 ...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
index d410dc05de1..f59d706473f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
@@ -13,20 +13,20 @@ body: |
     ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[ICMP]]
     ; GREEDY-LABEL: name: usube_s32_sss
     ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[USUBE:%[0-9]+]]:sgpr(s32), [[USUBE1:%[0-9]+]]:scc(s1) = G_USUBE [[COPY]], [[COPY1]], [[ICMP]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = COPY $sgpr1
     %2:_(s32) = COPY $sgpr2
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_USUBE %0, %1, %4
 ...
@@ -42,7 +42,7 @@ body: |
     ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
@@ -51,7 +51,7 @@ body: |
     ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
     ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
     ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
-    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i64 0
+    ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
     ; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
     ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
     ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
@@ -59,7 +59,7 @@ body: |
     %0:_(s32) = COPY $vgpr0
     %1:_(s32) = COPY $sgpr0
     %2:_(s32) = COPY $sgpr1
-    %3:_(s32) = G_CONSTANT i64 0
+    %3:_(s32) = G_CONSTANT i32 0
     %4:_(s1) = G_ICMP intpred(eq), %2, %3
     %5:_(s32), %6:_(s1) = G_USUBE %0, %1, %4
 ...