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| author | Geoff Berry <gberry@codeaurora.org> | 2018-01-30 17:37:39 +0000 |
|---|---|---|
| committer | Geoff Berry <gberry@codeaurora.org> | 2018-01-30 17:37:39 +0000 |
| commit | 1d531013876c02b18df678a5f67d6a7d94e392b9 (patch) | |
| tree | 0fd9364d1502ac5a80d423a64e1dcd987ac5e6ac /llvm/test/CodeGen/AMDGPU | |
| parent | c9265e81f491a3fc1b7b02920479bd34b236fac9 (diff) | |
| download | bcm5719-llvm-1d531013876c02b18df678a5f67d6a7d94e392b9.tar.gz bcm5719-llvm-1d531013876c02b18df678a5f67d6a7d94e392b9.zip | |
[AMDGPU] isRenamable fixes to support copy forwarding
Mark more opcodes as hasExtraSrcRegAllocReq so that their operands will
be marked as not renamable, to avoid copy forwarding violating the
constraint that only one operand may use the constant bus.
These changes fix a few mis-compiles when copy forwarding is enabled in
MachineCopyPropagation by D41835 (and were reviewed as part of that change).
llvm-svn: 323794
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/shrink-carry.mir | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-carry.mir b/llvm/test/CodeGen/AMDGPU/shrink-carry.mir index d499b2192e9..cf000ffa774 100644 --- a/llvm/test/CodeGen/AMDGPU/shrink-carry.mir +++ b/llvm/test/CodeGen/AMDGPU/shrink-carry.mir @@ -1,7 +1,7 @@ # RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s # GCN-LABEL: name: subbrev{{$}} -# GCN: V_SUBBREV_U32_e64 0, undef %vgpr0, killed renamable %vcc, implicit %exec +# GCN: V_SUBBREV_U32_e64 0, undef %vgpr0, killed %vcc, implicit %exec --- name: subbrev @@ -25,7 +25,7 @@ body: | ... # GCN-LABEL: name: subb{{$}} -# GCN: V_SUBB_U32_e64 undef %vgpr0, 0, killed renamable %vcc, implicit %exec +# GCN: V_SUBB_U32_e64 undef %vgpr0, 0, killed %vcc, implicit %exec --- name: subb @@ -49,7 +49,7 @@ body: | ... # GCN-LABEL: name: addc{{$}} -# GCN: V_ADDC_U32_e32 0, undef renamable %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec +# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec --- name: addc @@ -73,7 +73,7 @@ body: | ... # GCN-LABEL: name: addc2{{$}} -# GCN: V_ADDC_U32_e32 0, undef renamable %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec +# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec --- name: addc2 diff --git a/llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir b/llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir index d5bf6a1eb8c..8d3b8f242b8 100644 --- a/llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir +++ b/llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir @@ -9,7 +9,7 @@ # CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4, # CHECK-NEXT: stack-id: 1, -# CHECK: SI_SPILL_V32_SAVE killed renamable %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0) +# CHECK: SI_SPILL_V32_SAVE killed %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0) # CHECK: %vgpr0 = SI_SPILL_V32_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 4 from %stack.0) # CHECK: SI_SPILL_S32_SAVE killed renamable %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1) |
