[AMDGPU] Convert rcp to rcp_iflag

If a source of rcp instruction is a result of any conversion from
an integer convert it into rcp_iflag instruction. No FP exception
can ever happen except division by zero if a single precision rcp
argument is a representation of an integral number.

Differential Revision: https://reviews.llvm.org/D48569

llvm-svn: 335742

5 files changed, 43 insertions, 22 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/rcp_iflag.ll b/llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
new file mode 100644
index 00000000000..6fb680e6298
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/rcp_iflag.ll
@@ -0,0 +1,21 @@
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}rcp_uint:
+; GCN: v_rcp_iflag_f32_e32
+define amdgpu_kernel void @rcp_uint(i32 addrspace(1)* %in, float addrspace(1)* %out) {
+  %load = load i32, i32 addrspace(1)* %in, align 4
+  %cvt = uitofp i32 %load to float
+  %div = fdiv float 1.000000e+00, %cvt
+  store float %div, float addrspace(1)* %out, align 4
+  ret void
+}
+
+; GCN-LABEL: {{^}}rcp_sint:
+; GCN: v_rcp_iflag_f32_e32
+define amdgpu_kernel void @rcp_sint(i32 addrspace(1)* %in, float addrspace(1)* %out) {
+  %load = load i32, i32 addrspace(1)* %in, align 4
+  %cvt = sitofp i32 %load to float
+  %div = fdiv float 1.000000e+00, %cvt
+  store float %div, float addrspace(1)* %out, align 4
+  ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll
index b79bca54bbd..76fa6c5ce13 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll
@@ -84,7 +84,7 @@ define amdgpu_kernel void @sdiv_v4i32_4(<4 x i32> addrspace(1)* %out, <4 x i32>
 }
 
 ; FUNC-LABEL: {{^}}v_sdiv_i8:
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 8
 ; SI: buffer_store_dword [[BFE]]
 define amdgpu_kernel void @v_sdiv_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
@@ -98,7 +98,7 @@ define amdgpu_kernel void @v_sdiv_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %i
 }
 
 ; FUNC-LABEL: {{^}}v_sdiv_i23:
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 23
 ; SI: buffer_store_dword [[BFE]]
 define amdgpu_kernel void @v_sdiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)* %in) {
@@ -112,7 +112,7 @@ define amdgpu_kernel void @v_sdiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)*
 }
 
 ; FUNC-LABEL: {{^}}v_sdiv_i24:
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 24
 ; SI: buffer_store_dword [[BFE]]
 define amdgpu_kernel void @v_sdiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) {
diff --git a/llvm/test/CodeGen/AMDGPU/sdivrem24.ll b/llvm/test/CodeGen/AMDGPU/sdivrem24.ll
index 257e6be96b6..785a6f9d1db 100644
--- a/llvm/test/CodeGen/AMDGPU/sdivrem24.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdivrem24.ll
@@ -5,7 +5,7 @@
 ; FUNC-LABEL: {{^}}sdiv24_i8:
 ; SI: v_cvt_f32_i32
 ; SI: v_cvt_f32_i32
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_cvt_i32_f32
 
 ; EG: INT_TO_FLT
@@ -24,7 +24,7 @@ define amdgpu_kernel void @sdiv24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in
 ; FUNC-LABEL: {{^}}sdiv24_i16:
 ; SI: v_cvt_f32_i32
 ; SI: v_cvt_f32_i32
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_cvt_i32_f32
 
 ; EG: INT_TO_FLT
@@ -43,7 +43,7 @@ define amdgpu_kernel void @sdiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)*
 ; FUNC-LABEL: {{^}}sdiv24_i32:
 ; SI: v_cvt_f32_i32
 ; SI: v_cvt_f32_i32
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_cvt_i32_f32
 
 ; EG: INT_TO_FLT
@@ -123,7 +123,7 @@ define amdgpu_kernel void @test_no_sdiv24_i32_2(i32 addrspace(1)* %out, i32 addr
 ; FUNC-LABEL: {{^}}srem24_i8:
 ; SI: v_cvt_f32_i32
 ; SI: v_cvt_f32_i32
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_cvt_i32_f32
 
 ; EG: INT_TO_FLT
@@ -142,7 +142,7 @@ define amdgpu_kernel void @srem24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in
 ; FUNC-LABEL: {{^}}srem24_i16:
 ; SI: v_cvt_f32_i32
 ; SI: v_cvt_f32_i32
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_cvt_i32_f32
 
 ; EG: INT_TO_FLT
@@ -161,7 +161,7 @@ define amdgpu_kernel void @srem24_i16(i16 addrspace(1)* %out, i16 addrspace(1)*
 ; FUNC-LABEL: {{^}}srem24_i32:
 ; SI: v_cvt_f32_i32
 ; SI: v_cvt_f32_i32
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_cvt_i32_f32
 
 ; EG: INT_TO_FLT
@@ -278,7 +278,7 @@ define amdgpu_kernel void @no_srem25_i25_i24_i32(i32 addrspace(1)* %out, i32 add
 
 ; FUNC-LABEL: {{^}}srem25_i24_i11_i32:
 ; SI: v_cvt_f32_i32
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 24
 
 ; EG: INT_TO_FLT
@@ -298,7 +298,7 @@ define amdgpu_kernel void @srem25_i24_i11_i32(i32 addrspace(1)* %out, i32 addrsp
 
 ; FUNC-LABEL: {{^}}srem25_i11_i24_i32:
 ; SI: v_cvt_f32_i32
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 24
 
 ; EG: INT_TO_FLT
@@ -318,7 +318,7 @@ define amdgpu_kernel void @srem25_i11_i24_i32(i32 addrspace(1)* %out, i32 addrsp
 
 ; FUNC-LABEL: {{^}}srem25_i17_i12_i32:
 ; SI: v_cvt_f32_i32
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 17
 
 ; EG: INT_TO_FLT
diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll
index 1d683776bfd..00a240e173f 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv.ll
@@ -100,7 +100,7 @@ define amdgpu_kernel void @udiv_i32_div_k_odd(i32 addrspace(1)* %out, i32 addrsp
 }
 
 ; FUNC-LABEL: {{^}}v_udiv_i8:
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0xff, v{{[0-9]+}}
 ; SI: buffer_store_dword [[TRUNC]]
 define amdgpu_kernel void @v_udiv_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
@@ -114,7 +114,7 @@ define amdgpu_kernel void @v_udiv_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %i
 }
 
 ; FUNC-LABEL: {{^}}v_udiv_i16:
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0xffff, v{{[0-9]+}}
 ; SI: buffer_store_dword [[TRUNC]]
 define amdgpu_kernel void @v_udiv_i16(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
@@ -128,7 +128,7 @@ define amdgpu_kernel void @v_udiv_i16(i32 addrspace(1)* %out, i16 addrspace(1)*
 }
 
 ; FUNC-LABEL: {{^}}v_udiv_i23:
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0x7fffff, v{{[0-9]+}}
 ; SI: buffer_store_dword [[TRUNC]]
 define amdgpu_kernel void @v_udiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)* %in) {
diff --git a/llvm/test/CodeGen/AMDGPU/udivrem24.ll b/llvm/test/CodeGen/AMDGPU/udivrem24.ll
index 6f144dcc6fd..2c38f71f4b1 100644
--- a/llvm/test/CodeGen/AMDGPU/udivrem24.ll
+++ b/llvm/test/CodeGen/AMDGPU/udivrem24.ll
@@ -5,7 +5,7 @@
 ; FUNC-LABEL: {{^}}udiv24_i8:
 ; SI: v_cvt_f32_ubyte
 ; SI: v_cvt_f32_ubyte
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_cvt_u32_f32
 
 ; EG: UINT_TO_FLT
@@ -24,7 +24,7 @@ define amdgpu_kernel void @udiv24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in
 ; FUNC-LABEL: {{^}}udiv24_i16:
 ; SI: v_cvt_f32_u32
 ; SI: v_cvt_f32_u32
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_cvt_u32_f32
 
 ; EG: UINT_TO_FLT
@@ -43,7 +43,7 @@ define amdgpu_kernel void @udiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)*
 ; FUNC-LABEL: {{^}}udiv23_i32:
 ; SI: v_cvt_f32_u32
 ; SI-DAG: v_cvt_f32_u32
-; SI-DAG: v_rcp_f32
+; SI-DAG: v_rcp_iflag_f32
 ; SI: v_cvt_u32_f32
 
 ; EG: UINT_TO_FLT
@@ -177,7 +177,7 @@ define amdgpu_kernel void @test_no_udiv24_i32_2(i32 addrspace(1)* %out, i32 addr
 ; FUNC-LABEL: {{^}}urem24_i8:
 ; SI: v_cvt_f32_ubyte
 ; SI: v_cvt_f32_ubyte
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_cvt_u32_f32
 
 ; EG: UINT_TO_FLT
@@ -196,7 +196,7 @@ define amdgpu_kernel void @urem24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in
 ; FUNC-LABEL: {{^}}urem24_i16:
 ; SI: v_cvt_f32_u32
 ; SI: v_cvt_f32_u32
-; SI: v_rcp_f32
+; SI: v_rcp_iflag_f32
 ; SI: v_cvt_u32_f32
 
 ; EG: UINT_TO_FLT
@@ -289,7 +289,7 @@ define amdgpu_kernel void @test_no_urem24_i32_2(i32 addrspace(1)* %out, i32 addr
 }
 
 ; FUNC-LABEL: {{^}}test_udiv24_u16_u23_i32:
-; SI-DAG: v_rcp_f32
+; SI-DAG: v_rcp_iflag_f32
 ; SI-DAG: s_mov_b32 [[MASK:s[0-9]+]], 0x7fffff{{$}}
 ; SI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]],
 
@@ -308,7 +308,7 @@ define amdgpu_kernel void @test_udiv24_u16_u23_i32(i32 addrspace(1)* %out, i32 a
 }
 
 ; FUNC-LABEL: {{^}}test_udiv24_u23_u16_i32:
-; SI-DAG: v_rcp_f32
+; SI-DAG: v_rcp_iflag_f32
 ; SI-DAG: s_mov_b32 [[MASK:s[0-9]+]], 0x7fffff{{$}}
 ; SI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]],