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| author | Craig Topper <craig.topper@intel.com> | 2018-01-24 04:51:17 +0000 |
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| committer | Craig Topper <craig.topper@intel.com> | 2018-01-24 04:51:17 +0000 |
| commit | 0321ebc054c79d530f9f8626c2edf1bb317085c0 (patch) | |
| tree | 171e2a03bdbbdbef134c625a89b80925f778d6ab /llvm/test/CodeGen/AMDGPU | |
| parent | fcac3c9642d2609aa3c2adcafdd6ded178b0fa61 (diff) | |
| download | bcm5719-llvm-0321ebc054c79d530f9f8626c2edf1bb317085c0.tar.gz bcm5719-llvm-0321ebc054c79d530f9f8626c2edf1bb317085c0.zip | |
[X86] Use ISD::SIGN_EXTEND instead of X86ISD::VSEXT for mask to xmm/ymm/zmm conversion
There are a couple tricky things with this patch.
I had to add an override of isVectorLoadExtDesirable to stop DAG combine from combining sign_extend with loads after legalization since we legalize sextload using a load+sign_extend. Overriding this hook actually prevents a lot sextloads from being created in the first place.
I also had to add isel patterns because DAG combine blindly combines sign_extend+truncate to a smaller sign_extend which defeats what legalization was trying to do.
Differential Revision: https://reviews.llvm.org/D42407
llvm-svn: 323301
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
0 files changed, 0 insertions, 0 deletions
