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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-04-14 19:09:28 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-04-14 19:09:28 +0000 |
| commit | 000c5af3e65bcd32305d51a32ccdbe6fdf7d3fdf (patch) | |
| tree | 959ef307f75403f2bf48327f70012034022c5829 /llvm/test/CodeGen/AMDGPU | |
| parent | 3151d8959598d6da4f9373fc6965fedac16dc835 (diff) | |
| download | bcm5719-llvm-000c5af3e65bcd32305d51a32ccdbe6fdf7d3fdf.tar.gz bcm5719-llvm-000c5af3e65bcd32305d51a32ccdbe6fdf7d3fdf.zip | |
AMDGPU: Add skeleton GlobalIsel implementation
Summary:
This adds the necessary target code to be able to run the ir translator.
Lowering function arguments and returns is a nop and there is no support
for RegBankSelect.
Reviewers: arsenm, qcolombet
Subscribers: arsenm, joker.eph, vkalintiris, llvm-commits
Differential Revision: http://reviews.llvm.org/D19077
llvm-svn: 266356
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll new file mode 100644 index 00000000000..62b09dfedf1 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll @@ -0,0 +1,12 @@ +; RUN: llc -march=amdgcn -mcpu=fiji -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s +; REQUIRES: global-isel +; This file checks that the translation from llvm IR to generic MachineInstr +; is correct. + +; Tests for add. +; CHECK: name: addi32 +; CHECK: G_ADD i32 +define i32 @addi32(i32 %arg1, i32 %arg2) { + %res = add i32 %arg1, %arg2 + ret i32 %res +} |
