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| author | Simon Atanasyan <simon@atanasyan.com> | 2019-06-01 13:55:18 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2019-06-01 13:55:18 +0000 |
| commit | 25694e0084440f913f89c985b950948819215820 (patch) | |
| tree | 55b139de0ebb998f74414b585257876ceedcbc5f /llvm/test/CodeGen/AMDGPU/enqueue-kernel.ll | |
| parent | 45eb4c7e55341c0b83a21dedecc092e273795eda (diff) | |
| download | bcm5719-llvm-25694e0084440f913f89c985b950948819215820.tar.gz bcm5719-llvm-25694e0084440f913f89c985b950948819215820.zip | |
[mips] Extend range of register indexes accepted by cfcmsa/ctcmsa
The `cfcmsa` and `ctcmsa` instructions accept index of MSA control
register. The MIPS64 SIMD Architecture define eight MSA control
registers. But register index for `cfcmsa` and `ctcmsa` instructions
might be any number in 0..31 range. If the index is greater then 7,
`cfcmsa` writes zero to the destination registers and `ctcmsa` does
nothing [1].
[1] MIPS Architecture for Programmers Volume IV-j:
The MIPS64 SIMD Architecture Module
https://www.mips.com/?do-download=the-mips64-simd-architecture-module
Differential Revision: https://reviews.llvm.org/D62597
llvm-svn: 362299
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/enqueue-kernel.ll')
0 files changed, 0 insertions, 0 deletions

