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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-08 18:11:51 -0400 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2019-12-30 14:24:25 -0500 |
| commit | 7fa0bfe7d580e2b96b8d7f5bd0470287857e84cc (patch) | |
| tree | a8c579bc07bda84e7971460bc35be4ca7ecc3ffa /llvm/test/CodeGen/AMDGPU/GlobalISel | |
| parent | 94d08feaeff3591a36ed548ba7c732ddedd6f983 (diff) | |
| download | bcm5719-llvm-7fa0bfe7d580e2b96b8d7f5bd0470287857e84cc.tar.gz bcm5719-llvm-7fa0bfe7d580e2b96b8d7f5bd0470287857e84cc.zip | |
AMDGPU/GlobalISel: Select mul24 intrinsics
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/GlobalISel')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir new file mode 100644 index 00000000000..b5b9368ed4e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir @@ -0,0 +1,65 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s + +--- +name: mul_u24_vsv +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $sgpr0, $vgpr0 + ; GCN-LABEL: name: mul_u24_vsv + ; GCN: liveins: $sgpr0, $vgpr0 + ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], implicit $exec + ; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]] + %0:sgpr(s32) = COPY $sgpr0 + %1:vgpr(s32) = COPY $vgpr0 + %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1 + S_ENDPGM 0, implicit %2 +... + +--- +name: mul_u24_vvs +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $sgpr0, $vgpr0 + ; GCN-LABEL: name: mul_u24_vvs + ; GCN: liveins: $sgpr0, $vgpr0 + ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], implicit $exec + ; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:sgpr(s32) = COPY $sgpr0 + %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1 + S_ENDPGM 0, implicit %2 +... + +--- +name: mul_u24_vvv +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; GCN-LABEL: name: mul_u24_vvv + ; GCN: liveins: $vgpr0, $vgpr1 + ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], implicit $exec + ; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1 + S_ENDPGM 0, implicit %2 +... |
