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| author | Sanjay Patel <spatel@rotateright.com> | 2019-10-14 21:56:40 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2019-10-14 21:56:40 +0000 |
| commit | 1f40f15d54aac06421448b6de131231d2d78bc75 (patch) | |
| tree | da67f8a42ddd2b267bf4de0f8e48196c1e8e5ae1 /llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir | |
| parent | 9585d8c11a57f1d5038465ab8f90461c701053fb (diff) | |
| download | bcm5719-llvm-1f40f15d54aac06421448b6de131231d2d78bc75.tar.gz bcm5719-llvm-1f40f15d54aac06421448b6de131231d2d78bc75.zip | |
[InstCombine] fold a shifted bool zext to a select
For a constant shift amount, add the following fold.
shl (zext (i1 X)), ShAmt --> select (X, 1 << ShAmt, 0)
https://rise4fun.com/Alive/IZ9
Fixes PR42257.
Based on original patch by @zvi (Zvi Rackover)
Differential Revision: https://reviews.llvm.org/D63382
llvm-svn: 374828
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir')
0 files changed, 0 insertions, 0 deletions
