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| author | Jessica Paquette <jpaquette@apple.com> | 2018-12-07 22:08:02 +0000 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2018-12-07 22:08:02 +0000 |
| commit | cc4b6920b36f81ff3a4370c6646de07e268e838b (patch) | |
| tree | 5f3aa71c457678a744672ff72cc1d19e8ca13b5f /llvm/test/CodeGen/AArch64 | |
| parent | 2f5fd174c9718701c5c151b796cd4ff4faf1096f (diff) | |
| download | bcm5719-llvm-cc4b6920b36f81ff3a4370c6646de07e268e838b.tar.gz bcm5719-llvm-cc4b6920b36f81ff3a4370c6646de07e268e838b.zip | |
[GlobalISel] Add IR translation support for the @llvm.log10 intrinsic
This adds IR translation support for @llvm.log10 and updates relevant tests.
https://reviews.llvm.org/D55392
llvm-svn: 348657
Diffstat (limited to 'llvm/test/CodeGen/AArch64')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir | 3 |
2 files changed, 13 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 2997c5350eb..0d2300b23e6 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1396,6 +1396,16 @@ define float @test_log2_intrin(float %a) { ret float %res } +declare float @llvm.log10.f32(float) +define float @test_log10_intrin(float %a) { +; CHECK-LABEL: name: test_log10_intrin +; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0 +; CHECK: [[RES:%[0-9]+]]:_(s32) = G_FLOG10 [[A]] +; CHECK: $s0 = COPY [[RES]] + %res = call float @llvm.log10.f32(float %a) + ret float %res +} + declare float @llvm.fabs.f32(float) define float @test_fabs_intrin(float %a) { ; CHECK-LABEL: name: test_fabs_intrin diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir index 1bdd0f1b82a..a1d2ab9cb23 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir @@ -267,6 +267,9 @@ # DEBUG-NEXT: G_FLOG2 (opcode {{[0-9]+}}): 1 type index # DEBUG: .. type index coverage check SKIPPED: no rules defined # +# DEBUG-NEXT: G_FLOG10 (opcode {{[0-9]+}}): 1 type index +# DEBUG: .. type index coverage check SKIPPED: no rules defined +# # DEBUG-NEXT: G_FNEG (opcode {{[0-9]+}}): 1 type index # DEBUG: .. type index coverage check SKIPPED: no rules defined # |
