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authorClement Courbet <courbet@google.com>2019-11-22 09:07:55 +0100
committerClement Courbet <courbet@google.com>2019-11-22 14:47:18 +0100
commitcb15ba84fe7ca289ae561b0e770e7219da40e807 (patch)
tree37a0271fdd7c50424657fb1a51a7d3b259cc0561 /llvm/test/CodeGen/AArch64
parent1465b8bc3a2435eab46582616bdf7c6aee117e8d (diff)
downloadbcm5719-llvm-cb15ba84fe7ca289ae561b0e770e7219da40e807.tar.gz
bcm5719-llvm-cb15ba84fe7ca289ae561b0e770e7219da40e807.zip
Reland "[DAGCombiner] Allow zextended load combines."
Check that the generated type is simple.
Diffstat (limited to 'llvm/test/CodeGen/AArch64')
-rw-r--r--llvm/test/CodeGen/AArch64/load-combine-big-endian.ll12
-rw-r--r--llvm/test/CodeGen/AArch64/load-combine.ll12
2 files changed, 8 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/AArch64/load-combine-big-endian.ll b/llvm/test/CodeGen/AArch64/load-combine-big-endian.ll
index 426bb880ed1..19de95198c1 100644
--- a/llvm/test/CodeGen/AArch64/load-combine-big-endian.ll
+++ b/llvm/test/CodeGen/AArch64/load-combine-big-endian.ll
@@ -445,10 +445,9 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
define i32 @zext_load_i32_by_i8(i32* %arg) {
; CHECK-LABEL: zext_load_i32_by_i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: ldrb w9, [x0, #1]
-; CHECK-NEXT: bfi w8, w9, #8, #8
-; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: ldrh w8, [x0]
+; CHECK-NEXT: lsl w8, w8, #16
+; CHECK-NEXT: rev w0, w8
; CHECK-NEXT: ret
%tmp = bitcast i32* %arg to i8*
@@ -515,10 +514,7 @@ define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_bswap:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w8, [x0, #1]
-; CHECK-NEXT: ldrb w9, [x0]
-; CHECK-NEXT: bfi w8, w9, #8, #8
-; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: ldrh w0, [x0]
; CHECK-NEXT: ret
%tmp = bitcast i32* %arg to i8*
diff --git a/llvm/test/CodeGen/AArch64/load-combine.ll b/llvm/test/CodeGen/AArch64/load-combine.ll
index 906646cda15..066ecb21dc1 100644
--- a/llvm/test/CodeGen/AArch64/load-combine.ll
+++ b/llvm/test/CodeGen/AArch64/load-combine.ll
@@ -431,10 +431,7 @@ define i32 @load_i32_by_i8_base_offset_index_2(i8* %arg, i32 %i) {
define i32 @zext_load_i32_by_i8(i32* %arg) {
; CHECK-LABEL: zext_load_i32_by_i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w8, [x0]
-; CHECK-NEXT: ldrb w9, [x0, #1]
-; CHECK-NEXT: bfi w8, w9, #8, #8
-; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: ldrh w0, [x0]
; CHECK-NEXT: ret
%tmp = bitcast i32* %arg to i8*
@@ -501,10 +498,9 @@ define i32 @zext_load_i32_by_i8_shl_16(i32* %arg) {
define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
; CHECK-LABEL: zext_load_i32_by_i8_bswap:
; CHECK: // %bb.0:
-; CHECK-NEXT: ldrb w8, [x0, #1]
-; CHECK-NEXT: ldrb w9, [x0]
-; CHECK-NEXT: bfi w8, w9, #8, #8
-; CHECK-NEXT: mov w0, w8
+; CHECK-NEXT: ldrh w8, [x0]
+; CHECK-NEXT: lsl w8, w8, #16
+; CHECK-NEXT: rev w0, w8
; CHECK-NEXT: ret
%tmp = bitcast i32* %arg to i8*
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