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| author | Daniel Sanders <daniel_l_sanders@apple.com> | 2018-10-03 02:12:17 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2018-10-03 02:12:17 +0000 |
| commit | c973ad1878f335fbb90fd1ac421fa6309746fe53 (patch) | |
| tree | e7f10b7b21bc3568ee2298ef1fc21803b72829c2 /llvm/test/CodeGen/AArch64 | |
| parent | a01151294ae34da280379a76b4ba9a8f26c2e538 (diff) | |
| download | bcm5719-llvm-c973ad1878f335fbb90fd1ac421fa6309746fe53.tar.gz bcm5719-llvm-c973ad1878f335fbb90fd1ac421fa6309746fe53.zip | |
Re-commit: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
Summary: Depends on D45541
Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar, aemerson
Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45543
The previous commit failed portions of the test-suite on GreenDragon due to
duplicate COPY instructions and iterator invalidation. Both issues have now
been fixed. To assist with this, a helper (cloneVirtualRegister) has been added
to MachineRegisterInfo that can be used to get another register that has the same
type and class/bank as an existing one.
llvm-svn: 343654
Diffstat (limited to 'llvm/test/CodeGen/AArch64')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/O0-pipeline.ll | 1 |
3 files changed, 3 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index c0a1a2a149d..e1defd71958 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -54,7 +54,7 @@ false: } -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %0:_(s24) = G_LOAD %1:_(p0) :: (load 3 from `i24* undef`, align 1) (in function: odd_type_load) +; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(s32) = G_ZEXTLOAD %1:_(p0) :: (load 3 from `i24* undef`, align 1) (in function: odd_type_load) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type_load ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type_load define i32 @odd_type_load() { diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll index 40ddc68b817..65c9accb93d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll @@ -42,6 +42,7 @@ ; RUN: | FileCheck %s --check-prefix DISABLED ; ENABLED: IRTranslator +; ENABLED-NEXT: PreLegalizerCombiner ; VERIFY-NEXT: Verify generated machine code ; ENABLED-NEXT: Legalizer ; VERIFY-NEXT: Verify generated machine code diff --git a/llvm/test/CodeGen/AArch64/O0-pipeline.ll b/llvm/test/CodeGen/AArch64/O0-pipeline.ll index dd0d08e68e9..5121cf76ac4 100644 --- a/llvm/test/CodeGen/AArch64/O0-pipeline.ll +++ b/llvm/test/CodeGen/AArch64/O0-pipeline.ll @@ -33,6 +33,7 @@ ; CHECK-NEXT: Insert stack protectors ; CHECK-NEXT: Module Verifier ; CHECK-NEXT: IRTranslator +; CHECK-NEXT: AArch64PreLegalizerCombiner ; CHECK-NEXT: Legalizer ; CHECK-NEXT: RegBankSelect ; CHECK-NEXT: Localizer |
