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authorAlexey Bataev <a.bataev@hotmail.com>2015-07-15 08:39:35 +0000
committerAlexey Bataev <a.bataev@hotmail.com>2015-07-15 08:39:35 +0000
commitb9288601a3ec46c3b645818110038c9910efcc55 (patch)
tree4cdc6d11f707d00ce4e9a9fe705829bed8c01c6c /llvm/test/CodeGen/AArch64
parent5d36b230b5ea88cb6e06f604431f856808703969 (diff)
downloadbcm5719-llvm-b9288601a3ec46c3b645818110038c9910efcc55.tar.gz
bcm5719-llvm-b9288601a3ec46c3b645818110038c9910efcc55.zip
[SDAG] Optimize unordered comparison in soft-float mode (patch by Anton Nadolskiy)
Current implementation handles unordered comparison poorly in soft-float mode. Consider (a ULE b) which is a <= b. It is lowered to (ledf2(a, b) <= 0 || unorddf2(a, b) != 0) (in general). We can do better job by lowering it to (__gtdf2(a, b) <= 0). Such replacement is true for other CMP's (ult, ugt, uge). In general, we just call same function as for ordered case but negate comparison against zero. Differential Revision: http://reviews.llvm.org/D10804 llvm-svn: 242280
Diffstat (limited to 'llvm/test/CodeGen/AArch64')
-rw-r--r--llvm/test/CodeGen/AArch64/arm64-fp128.ll31
1 files changed, 8 insertions, 23 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-fp128.ll b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
index aaef39fcf51..097fe2ca6ed 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fp128.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
@@ -148,14 +148,9 @@ define i1 @test_setcc2() {
; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
%val = fcmp ugt fp128 %lhs, %rhs
-; CHECK: bl __gttf2
+; CHECK: bl __letf2
; CHECK: cmp w0, #0
-; CHECK: cset [[GT:w[0-9]+]], gt
-
-; CHECK: bl __unordtf2
-; CHECK: cmp w0, #0
-; CHECK: cset [[UNORDERED:w[0-9]+]], ne
-; CHECK: orr w0, [[UNORDERED]], [[GT]]
+; CHECK: cset w0, gt
ret i1 %val
; CHECK: ret
@@ -169,31 +164,21 @@ define i32 @test_br_cc() {
; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
- ; olt == !uge, which LLVM unfortunately "optimizes" this to.
+ ; olt == !uge, which LLVM optimizes this to.
%cond = fcmp olt fp128 %lhs, %rhs
-; CHECK: bl __getf2
-; CHECK: cmp w0, #0
-; CHECK: cset [[OGE:w[0-9]+]], ge
-
-; CHECK: bl __unordtf2
-; CHECK: cmp w0, #0
-; CHECK: cset [[UNORDERED:w[0-9]+]], ne
-
-; CHECK: orr [[UGE:w[0-9]+]], [[UNORDERED]], [[OGE]]
-; CHECK: cbnz [[UGE]], [[RET29:.LBB[0-9]+_[0-9]+]]
+; CHECK: bl __lttf2
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: b.ge {{.LBB[0-9]+_[0-9]+}}
br i1 %cond, label %iftrue, label %iffalse
iftrue:
ret i32 42
; CHECK-NEXT: BB#
; CHECK-NEXT: movz w0, #0x2a
-; CHECK-NEXT: b [[REALRET:.LBB[0-9]+_[0-9]+]]
-
+; CHECK: ret
iffalse:
ret i32 29
-; CHECK: [[RET29]]:
-; CHECK-NEXT: movz w0, #0x1d
-; CHECK-NEXT: [[REALRET]]:
+; CHECK: movz w0, #0x1d
; CHECK: ret
}
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