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author | Diogo N. Sampaio <diogo.sampaio@arm.com> | 2019-04-10 13:34:18 +0000 |
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committer | Diogo N. Sampaio <diogo.sampaio@arm.com> | 2019-04-10 13:34:18 +0000 |
commit | aae424a2d2669bc2167a6983fd0dba07fae40cff (patch) | |
tree | 64cad5545c508b902c165cacf044b6b18dff4e65 /llvm/test/CodeGen/AArch64 | |
parent | 71660b032164ab4ba9f0f3d74db77e032f0b09f6 (diff) | |
download | bcm5719-llvm-aae424a2d2669bc2167a6983fd0dba07fae40cff.tar.gz bcm5719-llvm-aae424a2d2669bc2167a6983fd0dba07fae40cff.zip |
[AArch64] Add lowering pattern for scalar fp16 facge and facgt
Summary: The fp16 scalar version of facge and facgt requires a custom patter matching, as the result type is not the same width of the operands.
Reviewers: olista01, javed.absar, pbarrio
Reviewed By: javed.absar
Subscribers: kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60212
llvm-svn: 358083
Diffstat (limited to 'llvm/test/CodeGen/AArch64')
-rw-r--r-- | llvm/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll b/llvm/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll index 13a18b10e9f..19365a6f2f7 100644 --- a/llvm/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll +++ b/llvm/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll @@ -7,6 +7,8 @@ declare half @llvm.aarch64.neon.frsqrts.f16(half, half) declare half @llvm.aarch64.neon.frecps.f16(half, half) declare half @llvm.aarch64.neon.fmulx.f16(half, half) declare half @llvm.fabs.f16(half) +declare i32 @llvm.aarch64.neon.facge.i32.f16(half, half) +declare i32 @llvm.aarch64.neon.facgt.i32.f16(half, half) define dso_local half @t_vabdh_f16(half %a, half %b) { ; CHECK-LABEL: t_vabdh_f16: @@ -318,3 +320,25 @@ entry: %vcvth_n_u32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 16) ret i32 %vcvth_n_u32_f16 } + +define dso_local i16 @vcageh_f16_test(half %a, half %b) { +; CHECK-LABEL: vcageh_f16_test: +; CHECK: facge h0, h0, h1 +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret +entry: + %facg = tail call i32 @llvm.aarch64.neon.facge.i32.f16(half %a, half %b) + %0 = trunc i32 %facg to i16 + ret i16 %0 +} + +define dso_local i16 @vcagth_f16_test(half %a, half %b) { +; CHECK-LABEL: vcagth_f16_test: +; CHECK: facgt h0, h0, h1 +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret +entry: + %facg = tail call i32 @llvm.aarch64.neon.facgt.i32.f16(half %a, half %b) + %0 = trunc i32 %facg to i16 + ret i16 %0 +} |