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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-16 10:00:45 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-06-16 10:00:45 +0000 |
| commit | 5e6f54e07b8ca0afd43b4bdeabedbf7071e02faa (patch) | |
| tree | f66a03e05233ca572d548f66068690cb80ec33ef /llvm/test/CodeGen/AArch64 | |
| parent | aee59aede291f65e78739fb2ab76972dbf058006 (diff) | |
| download | bcm5719-llvm-5e6f54e07b8ca0afd43b4bdeabedbf7071e02faa.tar.gz bcm5719-llvm-5e6f54e07b8ca0afd43b4bdeabedbf7071e02faa.zip | |
[mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rather than 16-bit in MIPS32r6/MIPS64r6
Summary:
The error message for the invalid.s cases isn't very helpful. It happens because
there is an instruction with a wider immediate that would have matched if the
NotMips32r6 predicate were true. I have some WIP to improve the message but it
affects most error messages for removed/re-encoded instructions on
MIPS32r6/MIPS64r6 and should therefore be a separate commit.
Depens on D4115
Reviewers: zoran.jovanovic, jkolek, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D4117
llvm-svn: 211012
Diffstat (limited to 'llvm/test/CodeGen/AArch64')
0 files changed, 0 insertions, 0 deletions
