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| author | Volkan Keles <vkeles@apple.com> | 2018-12-14 22:11:20 +0000 |
|---|---|---|
| committer | Volkan Keles <vkeles@apple.com> | 2018-12-14 22:11:20 +0000 |
| commit | 574d737e06fb9efc53b196536b3bf2124219d7e0 (patch) | |
| tree | 855b9d40506e95d2ac3e751cec81fc70a9d2c910 /llvm/test/CodeGen/AArch64 | |
| parent | c0fc0a9775c6e1f36d118744c41afd87fd182bef (diff) | |
| download | bcm5719-llvm-574d737e06fb9efc53b196536b3bf2124219d7e0.tar.gz bcm5719-llvm-574d737e06fb9efc53b196536b3bf2124219d7e0.zip | |
[GlobalISel] LegalizerHelper: Implement fewerElementsVector for G_LOAD/G_STORE
Reviewers: aemerson, dsanders, bogner, paquette, aditya_nandakumar
Reviewed By: dsanders
Subscribers: rovka, kristof.beyls, javed.absar, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53728
llvm-svn: 349200
Diffstat (limited to 'llvm/test/CodeGen/AArch64')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-fewerElts.mir | 39 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir | 54 |
2 files changed, 54 insertions, 39 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-fewerElts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-fewerElts.mir deleted file mode 100644 index 7f42f6e6c33..00000000000 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-fewerElts.mir +++ /dev/null @@ -1,39 +0,0 @@ -# RUN: llc -march=aarch64 -o - -run-pass=legalizer -global-isel-abort=0 -debug-only=legalizer 2>&1 %s | FileCheck %s -# REQUIRES: asserts - -# CHECK: Legalize Machine IR for: load_v4s32 -# CHECK-NEXT: %{{[0-9]+}}:_(<4 x s32>) = G_LOAD %{{[0-9]+}}:_(p0) -# CHECK-NEXT: Reduce number of elements ---- -name: load_v4s32 -legalized: false -tracksRegLiveness: true -body: | - bb.1: - liveins: $x0 - - %0:_(p0) = COPY $x0 - %1:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16, align 4) - %2:_(s32), %3:_(s32), %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %1(<4 x s32>) - $w0 = COPY %5(s32) - -... - -# Make sure we are able to scalarize v2s64. -# CHECK: Legalize Machine IR for: load_v2s64 -# CHECK-NEXT: %{{[0-9]+}}:_(<2 x s64>) = G_LOAD %{{[0-9]+}}:_(p0) -# CHECK-NEXT: Reduce number of elements ---- -name: load_v2s64 -legalized: false -tracksRegLiveness: true -body: | - bb.1: - liveins: $x0 - - %0:_(p0) = COPY $x0 - %1:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16) - %2:_(s64), %3:_(s64) = G_UNMERGE_VALUES %1(<2 x s64>) - $x0 = COPY %3(s64) - -... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir new file mode 100644 index 00000000000..27791881ef3 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir @@ -0,0 +1,54 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=aarch64 -o - -run-pass=legalizer %s | FileCheck %s +--- +name: load_v4s32 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x0, $x1 + + ; CHECK-LABEL: name: load_v4s32 + ; CHECK: liveins: $x0, $x1 + ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 + ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load 8, align 16) + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64) + ; CHECK: [[LOAD1:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[GEP]](p0) :: (load 8) + ; CHECK: G_STORE [[LOAD]](<2 x s32>), [[COPY1]](p0) :: (store 8, align 16) + ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s64) + ; CHECK: G_STORE [[LOAD1]](<2 x s32>), [[GEP1]](p0) :: (store 8) + %0:_(p0) = COPY $x0 + %1:_(p0) = COPY $x1 + %2:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16) + G_STORE %2(<4 x s32>), %1(p0) :: (store 16) + +... +--- +name: load_v2s64 +legalized: false +tracksRegLiveness: true +body: | + bb.1: + liveins: $x0, $x1 + + ; CHECK-LABEL: name: load_v2s64 + ; CHECK: liveins: $x0, $x1 + ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 + ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8, align 16) + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64) + ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8) + ; CHECK: G_STORE [[LOAD]](s64), [[COPY1]](p0) :: (store 8, align 16) + ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s64) + ; CHECK: G_STORE [[LOAD1]](s64), [[GEP1]](p0) :: (store 8) + %0:_(p0) = COPY $x0 + %1:_(p0) = COPY $x1 + %2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16) + G_STORE %2(<2 x s64>), %1(p0) :: (store 16) + +... |

