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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-10-07 11:24:04 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-10-07 11:24:04 +0000 |
| commit | 012fda59a5b47e52e8f766c30a661c620a8cca50 (patch) | |
| tree | a2118f772cdd3a1d2974dc560d514803e032d925 /llvm/test/CodeGen/AArch64 | |
| parent | e4d199e36000718840d0f003c9060ef63eddb1eb (diff) | |
| download | bcm5719-llvm-012fda59a5b47e52e8f766c30a661c620a8cca50.tar.gz bcm5719-llvm-012fda59a5b47e52e8f766c30a661c620a8cca50.zip | |
[AARCH64][X86] Remove _nonsplat from test names
As discussed on D50222
llvm-svn: 343934
Diffstat (limited to 'llvm/test/CodeGen/AArch64')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll b/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll index 726f4083761..57d41d6fa89 100644 --- a/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll +++ b/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll @@ -3,8 +3,8 @@ ; At the moment, BuildUREMEqFold does not handle nonsplat vectors. -define <4 x i32> @test_urem_odd_div_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-LABEL: test_urem_odd_div_nonsplat: +define <4 x i32> @test_urem_odd_div(<4 x i32> %X) nounwind readnone { +; CHECK-LABEL: test_urem_odd_div: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI0_0 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0] @@ -35,8 +35,8 @@ define <4 x i32> @test_urem_odd_div_nonsplat(<4 x i32> %X) nounwind readnone { ret <4 x i32> %ret } -define <4 x i32> @test_urem_even_div_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-LABEL: test_urem_even_div_nonsplat: +define <4 x i32> @test_urem_even_div(<4 x i32> %X) nounwind readnone { +; CHECK-LABEL: test_urem_even_div: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI1_0 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0] @@ -64,8 +64,8 @@ define <4 x i32> @test_urem_even_div_nonsplat(<4 x i32> %X) nounwind readnone { ret <4 x i32> %ret } -define <4 x i32> @test_urem_pow2_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-LABEL: test_urem_pow2_nonsplat: +define <4 x i32> @test_urem_pow2(<4 x i32> %X) nounwind readnone { +; CHECK-LABEL: test_urem_pow2: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI2_0 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0] @@ -89,8 +89,8 @@ define <4 x i32> @test_urem_pow2_nonsplat(<4 x i32> %X) nounwind readnone { ret <4 x i32> %ret } -define <4 x i32> @test_urem_one_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-LABEL: test_urem_one_nonsplat: +define <4 x i32> @test_urem_one(<4 x i32> %X) nounwind readnone { +; CHECK-LABEL: test_urem_one: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI3_0 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0] @@ -121,8 +121,8 @@ define <4 x i32> @test_urem_one_nonsplat(<4 x i32> %X) nounwind readnone { ret <4 x i32> %ret } -define <4 x i32> @test_urem_comp_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-LABEL: test_urem_comp_nonsplat: +define <4 x i32> @test_urem_comp(<4 x i32> %X) nounwind readnone { +; CHECK-LABEL: test_urem_comp: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #52429 ; CHECK-NEXT: movk w8, #52428, lsl #16 @@ -145,8 +145,8 @@ define <4 x i32> @test_urem_comp_nonsplat(<4 x i32> %X) nounwind readnone { ret <4 x i32> %ret } -define <4 x i32> @test_urem_both_nonsplat(<4 x i32> %X) nounwind readnone { -; CHECK-LABEL: test_urem_both_nonsplat: +define <4 x i32> @test_urem_both(<4 x i32> %X) nounwind readnone { +; CHECK-LABEL: test_urem_both: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI5_0 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0] |
