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authorSimon Pilgrim <llvm-dev@redking.me.uk>2016-07-10 22:26:05 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2016-07-10 22:26:05 +0000
commitee4a33ae465d0b2bf1771af93871bac41da8d9dc (patch)
tree7f18e2bb95caf9fa5937d2192efc27ce4caa3b0d /llvm/lib
parentd66a7b05dbdc42f9894e0ef5bbba4ff8c37d1e6d (diff)
downloadbcm5719-llvm-ee4a33ae465d0b2bf1771af93871bac41da8d9dc.tar.gz
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[X86][SSE] Relax type assertions for matchVectorShuffleAsInsertPS
Calls to matchVectorShuffleAsInsertPS only need to ensure the inputs are 128-bit vectors. Only lowerVectorShuffleAsInsertPS needs to ensure that they are v4f32. llvm-svn: 275028
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 97103504198..4cbffcc2f21 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -8692,8 +8692,8 @@ static bool matchVectorShuffleAsInsertPS(SDValue &V1, SDValue &V2,
const SmallBitVector &Zeroable,
ArrayRef<int> Mask,
SelectionDAG &DAG) {
- assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
- assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
+ assert(V1.getSimpleValueType().is128BitVector() && "Bad operand type!");
+ assert(V2.getSimpleValueType().is128BitVector() && "Bad operand type!");
assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
unsigned ZMask = 0;
int V1DstIndex = -1;
@@ -8757,6 +8757,8 @@ static bool matchVectorShuffleAsInsertPS(SDValue &V1, SDValue &V2,
static SDValue lowerVectorShuffleAsInsertPS(const SDLoc &DL, SDValue V1,
SDValue V2, ArrayRef<int> Mask,
SelectionDAG &DAG) {
+ assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
+ assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
// Attempt to match the insertps pattern.
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