From ee4a33ae465d0b2bf1771af93871bac41da8d9dc Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 10 Jul 2016 22:26:05 +0000 Subject: [X86][SSE] Relax type assertions for matchVectorShuffleAsInsertPS Calls to matchVectorShuffleAsInsertPS only need to ensure the inputs are 128-bit vectors. Only lowerVectorShuffleAsInsertPS needs to ensure that they are v4f32. llvm-svn: 275028 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'llvm/lib') diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 97103504198..4cbffcc2f21 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -8692,8 +8692,8 @@ static bool matchVectorShuffleAsInsertPS(SDValue &V1, SDValue &V2, const SmallBitVector &Zeroable, ArrayRef Mask, SelectionDAG &DAG) { - assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!"); - assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!"); + assert(V1.getSimpleValueType().is128BitVector() && "Bad operand type!"); + assert(V2.getSimpleValueType().is128BitVector() && "Bad operand type!"); assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!"); unsigned ZMask = 0; int V1DstIndex = -1; @@ -8757,6 +8757,8 @@ static bool matchVectorShuffleAsInsertPS(SDValue &V1, SDValue &V2, static SDValue lowerVectorShuffleAsInsertPS(const SDLoc &DL, SDValue V1, SDValue V2, ArrayRef Mask, SelectionDAG &DAG) { + assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!"); + assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!"); SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2); // Attempt to match the insertps pattern. -- cgit v1.2.3