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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-03-24 16:07:30 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-03-24 16:07:30 +0000 |
| commit | da99c6eff5f50b8fb7642fb0db59bbd1d5092913 (patch) | |
| tree | 427810ce0ec450218ec9c3248cd4de9d31ffa185 /llvm/lib | |
| parent | c9a67a2b6d65b15ce3aae9ec00eda255751d851d (diff) | |
| download | bcm5719-llvm-da99c6eff5f50b8fb7642fb0db59bbd1d5092913.tar.gz bcm5719-llvm-da99c6eff5f50b8fb7642fb0db59bbd1d5092913.zip | |
R600/SI: Promote fp64 SELECT to i64
This type promotion is replacing a Tablegen pattern and it is already
covered by existing tests.
llvm-svn: 204617
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 12 |
2 files changed, 2 insertions, 12 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index fd1e3a69bd1..47376b40286 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -104,6 +104,8 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : setOperationAction(ISD::STORE, MVT::v4i32, Custom); setOperationAction(ISD::SELECT, MVT::i64, Custom); + setOperationAction(ISD::SELECT, MVT::f64, Promote); + AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64); setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index eb10541b6f2..8ec29713e07 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -904,18 +904,6 @@ def : Pat < (EXTRACT_SUBREG $val, sub0) >; -//use two V_CNDMASK_B32_e64 instructions for f64 -def : Pat < - (f64 (select i1:$src2, f64:$src1, f64:$src0)), - (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), - (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub0), - (EXTRACT_SUBREG $src1, sub0), - $src2), sub0), - (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub1), - (EXTRACT_SUBREG $src1, sub1), - $src2), sub1) ->; - def V_READLANE_B32 : VOP2 < 0x00000001, (outs SReg_32:$vdst), |
