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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-03-24 16:07:28 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-03-24 16:07:28 +0000 |
| commit | c9a67a2b6d65b15ce3aae9ec00eda255751d851d (patch) | |
| tree | 0a19b5265a959ba3fb3d38515095e5454fc21c76 /llvm/lib | |
| parent | 2c1c9de1515c1fa98426702196f4a9895a0450c5 (diff) | |
| download | bcm5719-llvm-c9a67a2b6d65b15ce3aae9ec00eda255751d851d.tar.gz bcm5719-llvm-c9a67a2b6d65b15ce3aae9ec00eda255751d851d.zip | |
SelectionDAG: Allow promotion of SELECT nodes from float to int types
And vice-versa, as long as the types are the same width.
There are a few R600 tests that will cover this.
llvm-svn: 204616
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 6297774484f..74c01cae437 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3990,7 +3990,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) { } case ISD::SELECT: { unsigned ExtOp, TruncOp; - if (Node->getValueType(0).isVector()) { + if (Node->getValueType(0).isVector() || + Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) { ExtOp = ISD::BITCAST; TruncOp = ISD::BITCAST; } else if (Node->getValueType(0).isInteger()) { |
