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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-05-18 14:34:51 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-05-18 14:34:51 +0000
commitca3b532e2cb00748e79bb1a20887678219dcb606 (patch)
treee1ca1e6cee72aa37733f2b4c39596b6d6aad2a62 /llvm/lib
parenta090864762402f7ce1d8639e90c49ea574a3d8f8 (diff)
downloadbcm5719-llvm-ca3b532e2cb00748e79bb1a20887678219dcb606.tar.gz
bcm5719-llvm-ca3b532e2cb00748e79bb1a20887678219dcb606.zip
[Hexagon] Recognize "q" and "v" in inline-asm as register constraints
llvm-svn: 269933
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLowering.cpp14
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLowering.h4
2 files changed, 16 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index f49a984463b..83e71cbecc8 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2839,6 +2839,20 @@ HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
// Inline Assembly Support
//===----------------------------------------------------------------------===//
+TargetLowering::ConstraintType
+HexagonTargetLowering::getConstraintType(StringRef Constraint) const {
+ if (Constraint.size() == 1) {
+ switch (Constraint[0]) {
+ case 'q':
+ case 'v':
+ if (Subtarget.useHVXOps())
+ return C_Register;
+ break;
+ }
+ }
+ return TargetLowering::getConstraintType(Constraint);
+}
+
std::pair<unsigned, const TargetRegisterClass *>
HexagonTargetLowering::getRegForInlineAsmConstraint(
const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index 50af2ade765..6d85068e5bb 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -203,6 +203,8 @@ bool isPositiveHalfWord(SDNode *N);
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const override;
+ ConstraintType getConstraintType(StringRef Constraint) const override;
+
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
StringRef Constraint, MVT VT) const override;
@@ -211,8 +213,6 @@ bool isPositiveHalfWord(SDNode *N);
getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "o")
return InlineAsm::Constraint_o;
- else if (ConstraintCode == "v")
- return InlineAsm::Constraint_v;
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}
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