diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.h | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/inline-asm-qv.ll | 19 |
3 files changed, 35 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index f49a984463b..83e71cbecc8 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2839,6 +2839,20 @@ HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // Inline Assembly Support //===----------------------------------------------------------------------===// +TargetLowering::ConstraintType +HexagonTargetLowering::getConstraintType(StringRef Constraint) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + case 'q': + case 'v': + if (Subtarget.useHVXOps()) + return C_Register; + break; + } + } + return TargetLowering::getConstraintType(Constraint); +} + std::pair<unsigned, const TargetRegisterClass *> HexagonTargetLowering::getRegForInlineAsmConstraint( const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index 50af2ade765..6d85068e5bb 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -203,6 +203,8 @@ bool isPositiveHalfWord(SDNode *N); ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override; + ConstraintType getConstraintType(StringRef Constraint) const override; + std::pair<unsigned, const TargetRegisterClass *> getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override; @@ -211,8 +213,6 @@ bool isPositiveHalfWord(SDNode *N); getInlineAsmMemConstraint(StringRef ConstraintCode) const override { if (ConstraintCode == "o") return InlineAsm::Constraint_o; - else if (ConstraintCode == "v") - return InlineAsm::Constraint_v; return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); } diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll new file mode 100644 index 00000000000..25634217031 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Check that constraints q and v are handled correctly. +; CHECK: q{{.}} = vgtw(v{{.}}.w,v{{.}}.w) +; CHECK: vand +; CHECK: vmem + +target triple = "hexagon" + +; Function Attrs: nounwind +define void @foo(<16 x i32> %v0, <16 x i32> %v1, <16 x i32>* nocapture %p) #0 { +entry: + %0 = tail call <16 x i32> asm "$0 = vgtw($1.w,$2.w)", "=q,v,v"(<16 x i32> %v0, <16 x i32> %v1) #1 + store <16 x i32> %0, <16 x i32>* %p, align 64 + ret void +} + +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #1 = { nounwind readnone } |
