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| author | Bob Wilson <bob.wilson@apple.com> | 2010-12-17 01:21:12 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-12-17 01:21:12 +0000 |
| commit | bfc6904fc65434ab2216807248918d9dacafe6ee (patch) | |
| tree | df3c69b25b034e04cf7c24e21994a2a37f839ee5 /llvm/lib | |
| parent | 261aad8e169cd93958651be86d4c3bbb654e26c9 (diff) | |
| download | bcm5719-llvm-bfc6904fc65434ab2216807248918d9dacafe6ee.tar.gz bcm5719-llvm-bfc6904fc65434ab2216807248918d9dacafe6ee.zip | |
Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.
Radar 8776599
llvm-svn: 122018
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | 7 |
2 files changed, 6 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 3ba8b3690ad..86f88f1f179 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -543,9 +543,7 @@ void InstrEmitter::EmitRegSequence(SDNode *Node, const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); const TargetRegisterClass *SRC = TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); - if (!SRC) - llvm_unreachable("Invalid subregister index in REG_SEQUENCE"); - if (SRC != RC) { + if (SRC && SRC != RC) { MRI->setRegClass(NewVReg, SRC); RC = SRC; } diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 60086ce224e..d74d2da6b77 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -1417,6 +1417,7 @@ bool TwoAddressInstructionPass::EliminateRegSequences() { SmallSet<unsigned, 4> Seen; for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { unsigned SrcReg = MI->getOperand(i).getReg(); + unsigned SubIdx = MI->getOperand(i+1).getImm(); if (MI->getOperand(i).getSubReg() || TargetRegisterInfo::isPhysicalRegister(SrcReg)) { DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); @@ -1436,7 +1437,9 @@ bool TwoAddressInstructionPass::EliminateRegSequences() { bool isKill = MI->getOperand(i).isKill(); if (!Seen.insert(SrcReg) || MI->getParent() != DefMI->getParent() || - !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI)) { + !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) || + !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), + MRI->getRegClass(SrcReg), SubIdx)) { // REG_SEQUENCE cannot have duplicated operands, add a copy. // Also add an copy if the source is live-in the block. We don't want // to end up with a partial-redef of a livein, e.g. @@ -1465,7 +1468,7 @@ bool TwoAddressInstructionPass::EliminateRegSequences() { MachineBasicBlock::iterator InsertLoc = MI; MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc, MI->getDebugLoc(), TII->get(TargetOpcode::COPY)) - .addReg(DstReg, RegState::Define, MI->getOperand(i+1).getImm()) + .addReg(DstReg, RegState::Define, SubIdx) .addReg(SrcReg, getKillRegState(isKill)); MI->getOperand(i).setReg(0); if (LV && isKill) |
