diff options
| author | Daniel Kiss <daniel.kiss@arm.com> | 2020-06-15 15:02:38 +0200 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2020-06-16 20:05:15 -0700 |
| commit | bf89c5aeb8915d488fa1c790e1b237b62a49c01f (patch) | |
| tree | 86b6103aeb8acac688066a5ed17dba0f6f5dbec3 /llvm/lib | |
| parent | aab50695971617d37ad420b476671995f7078e79 (diff) | |
| download | bcm5719-llvm-bf89c5aeb8915d488fa1c790e1b237b62a49c01f.tar.gz bcm5719-llvm-bf89c5aeb8915d488fa1c790e1b237b62a49c01f.zip | |
[AArch64] Fix BTI instruction emission.
Summary:
SCTLR_EL1.BT[01] controls the PACI[AB]SP compatibility with PBYTE 11
(see [1])
This bit will be set to zero so PACI[AB]SP are equal to BTI C
instruction only.
[1] https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/sctlr_el1
Reviewers: chill, tamas.petz, pbarrio, ostannard
Reviewed By: tamas.petz, ostannard
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D81746
(cherry picked from commit b8ae3fdfa579dbf366b1bb1cbfdbf8c51db7fa55)
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64BranchTargets.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp b/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp index be6450c9a45..1956014b738 100644 --- a/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp +++ b/llvm/lib/Target/AArch64/AArch64BranchTargets.cpp @@ -122,9 +122,11 @@ void AArch64BranchTargets::addBTI(MachineBasicBlock &MBB, bool CouldCall, for (; MBBI != MBB.end() && MBBI->isMetaInstruction(); ++MBBI) ; - // PACI[AB]SP are implicitly BTI JC, so no BTI instruction needed there. - if (MBBI != MBB.end() && (MBBI->getOpcode() == AArch64::PACIASP || - MBBI->getOpcode() == AArch64::PACIBSP)) + // SCTLR_EL1.BT[01] is set to 0 by default which means + // PACI[AB]SP are implicitly BTI C so no BTI C instruction is needed there. + if (MBBI != MBB.end() && HintNum == 34 && + (MBBI->getOpcode() == AArch64::PACIASP || + MBBI->getOpcode() == AArch64::PACIBSP)) return; BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()), |
