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| author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2014-12-01 11:12:04 +0000 |
|---|---|---|
| committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2014-12-01 11:12:04 +0000 |
| commit | b682ddf33ae05386c7069877abf2cd74ea89c13a (patch) | |
| tree | 200d56cb61021e63c469234de356b3401e5d00eb /llvm/lib | |
| parent | a056ac8a9823a60d85e0dfed2a0cee6c659d0f39 (diff) | |
| download | bcm5719-llvm-b682ddf33ae05386c7069877abf2cd74ea89c13a.tar.gz bcm5719-llvm-b682ddf33ae05386c7069877abf2cd74ea89c13a.zip | |
The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.
llvm-svn: 223006
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 39 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 3 |
2 files changed, 42 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 878bc23dbab..81bbe3003e2 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -340,6 +340,15 @@ static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + +static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't /// handle. template <typename InsnType> @@ -1591,6 +1600,36 @@ static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, return MCDisassembler::Success; } +static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + int32_t DecodedValue; + switch (Insn) { + case 0: DecodedValue = 256; break; + case 1: DecodedValue = 257; break; + case 510: DecodedValue = -258; break; + case 511: DecodedValue = -257; break; + default: DecodedValue = SignExtend32<9>(Insn); break; + } + Inst.addOperand(MCOperand::CreateImm(DecodedValue << 2)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + // Insn must be >= 0, since it is unsigned that condition is always true. + assert(Insn < 16); + int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, + 255, 32768, 65535}; + Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn])); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + Inst.addOperand(MCOperand::CreateImm(Insn << 2)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 209cff1c66a..11ce41adf1d 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -13,6 +13,7 @@ def simm12 : Operand<i32> { def uimm5_lsl2 : Operand<OtherVT> { let EncoderMethod = "getUImm5Lsl2Encoding"; + let DecoderMethod = "DecodeUImm5lsl2"; } def uimm6_lsl2 : Operand<i32> { @@ -22,6 +23,7 @@ def uimm6_lsl2 : Operand<i32> { def simm9_addiusp : Operand<i32> { let EncoderMethod = "getSImm9AddiuspValue"; + let DecoderMethod = "DecodeSimm9SP"; } def uimm3_shift : Operand<i32> { @@ -35,6 +37,7 @@ def simm3_lsa2 : Operand<i32> { def uimm4_andi : Operand<i32> { let EncoderMethod = "getUImm4AndValue"; + let DecoderMethod = "DecodeANDI16Imm"; } def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 || |
