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authorVladimir Medic <Vladimir.Medic@imgtec.com>2014-12-01 11:12:04 +0000
committerVladimir Medic <Vladimir.Medic@imgtec.com>2014-12-01 11:12:04 +0000
commitb682ddf33ae05386c7069877abf2cd74ea89c13a (patch)
tree200d56cb61021e63c469234de356b3401e5d00eb /llvm
parenta056ac8a9823a60d85e0dfed2a0cee6c659d0f39 (diff)
downloadbcm5719-llvm-b682ddf33ae05386c7069877abf2cd74ea89c13a.tar.gz
bcm5719-llvm-b682ddf33ae05386c7069877abf2cd74ea89c13a.zip
The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.
llvm-svn: 223006
Diffstat (limited to 'llvm')
-rw-r--r--llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp39
-rw-r--r--llvm/lib/Target/Mips/MicroMipsInstrInfo.td3
-rw-r--r--llvm/test/MC/Disassembler/Mips/micromips.txt21
-rw-r--r--llvm/test/MC/Disassembler/Mips/micromips_le.txt21
-rw-r--r--llvm/test/MC/Mips/micromips-16-bit-instructions.s12
5 files changed, 96 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index 878bc23dbab..81bbe3003e2 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -340,6 +340,15 @@ static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+
+static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
+
/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
/// handle.
template <typename InsnType>
@@ -1591,6 +1600,36 @@ static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ int32_t DecodedValue;
+ switch (Insn) {
+ case 0: DecodedValue = 256; break;
+ case 1: DecodedValue = 257; break;
+ case 510: DecodedValue = -258; break;
+ case 511: DecodedValue = -257; break;
+ default: DecodedValue = SignExtend32<9>(Insn); break;
+ }
+ Inst.addOperand(MCOperand::CreateImm(DecodedValue << 2));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ // Insn must be >= 0, since it is unsigned that condition is always true.
+ assert(Insn < 16);
+ int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
+ 255, 32768, 65535};
+ Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ Inst.addOperand(MCOperand::CreateImm(Insn << 2));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeRegListOperand(MCInst &Inst,
unsigned Insn,
uint64_t Address,
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index 209cff1c66a..11ce41adf1d 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -13,6 +13,7 @@ def simm12 : Operand<i32> {
def uimm5_lsl2 : Operand<OtherVT> {
let EncoderMethod = "getUImm5Lsl2Encoding";
+ let DecoderMethod = "DecodeUImm5lsl2";
}
def uimm6_lsl2 : Operand<i32> {
@@ -22,6 +23,7 @@ def uimm6_lsl2 : Operand<i32> {
def simm9_addiusp : Operand<i32> {
let EncoderMethod = "getSImm9AddiuspValue";
+ let DecoderMethod = "DecodeSimm9SP";
}
def uimm3_shift : Operand<i32> {
@@ -35,6 +37,7 @@ def simm3_lsa2 : Operand<i32> {
def uimm4_andi : Operand<i32> {
let EncoderMethod = "getUImm4AndValue";
+ let DecoderMethod = "DecodeANDI16Imm";
}
def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
diff --git a/llvm/test/MC/Disassembler/Mips/micromips.txt b/llvm/test/MC/Disassembler/Mips/micromips.txt
index 7529d266dc7..164f5396df9 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips.txt
@@ -16,6 +16,21 @@
# CHECK: addiu $9, $6, -15001
0x31 0x26 0xc5 0x67
+# CHECK: addiusp -16
+0x4f 0xf9
+
+# CHECK: addiusp -1028
+0x4f 0xff
+
+# CHECK: addiusp -1032
+0x4f 0xfd
+
+# CHECK: addiusp 1024
+0x4c 0x01
+
+# CHECK: addiusp 1028
+0x4c 0x03
+
# CHECK: addu $9, $6, $7
0x00 0xe6 0x49 0x50
@@ -61,6 +76,9 @@
# CHECK: andi $9, $6, 17767
0xd1 0x26 0x45 0x67
+# CHECK: andi16 $16, $2, 31
+0x2c 0x29
+
# CHECK: or $3, $4, $5
0x00 0xa4 0x1a 0x90
@@ -229,6 +247,9 @@
# CHECK: jr $7
0x00 0x07 0x0f 0x3c
+# CHECK: jraddiusp 20
+0x47 0x05
+
# CHECK: beq $9, $6, 1332
0x94 0xc9 0x02 0x9a
diff --git a/llvm/test/MC/Disassembler/Mips/micromips_le.txt b/llvm/test/MC/Disassembler/Mips/micromips_le.txt
index 10bd7c3b23b..39be8dc57b6 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips_le.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips_le.txt
@@ -16,9 +16,27 @@
# CHECK: addiu $9, $6, -15001
0x26 0x31 0x67 0xc5
+# CHECK: addiusp -16
+0xf9 0x4f
+
+# CHECK: addiusp -1028
+0xff 0x4f
+
+# CHECK: addiusp -1032
+0xfd 0x4f
+
+# CHECK: addiusp 1024
+0x01 0x4c
+
+# CHECK: addiusp 1028
+0x03 0x4c
+
# CHECK: addu $9, $6, $7
0xe6 0x00 0x50 0x49
+# CHECK: andi16 $16, $2, 31
+0x29 0x2c
+
# CHECK: sub $9, $6, $7
0xe6 0x00 0x90 0x49
@@ -229,6 +247,9 @@
# CHECK: jr $7
0x07 0x00 0x3c 0x0f
+# CHECK: jraddiusp 20
+0x05 0x47
+
# CHECK: beq $9, $6, 1332
0xc9 0x94 0x9a 0x02
diff --git a/llvm/test/MC/Mips/micromips-16-bit-instructions.s b/llvm/test/MC/Mips/micromips-16-bit-instructions.s
index a21c4c99d5e..7ff6d9d4c50 100644
--- a/llvm/test/MC/Mips/micromips-16-bit-instructions.s
+++ b/llvm/test/MC/Mips/micromips-16-bit-instructions.s
@@ -32,6 +32,10 @@
# CHECK-EL: addiur2 $6, $7, -1 # encoding: [0x7e,0x6f]
# CHECK-EL: addiur2 $6, $7, 12 # encoding: [0x76,0x6f]
# CHECK-EL: addius5 $7, -2 # encoding: [0xfc,0x4c]
+# CHECK-EL: addiusp -1028 # encoding: [0xff,0x4f]
+# CHECK-EL: addiusp -1032 # encoding: [0xfd,0x4f]
+# CHECK-EL: addiusp 1024 # encoding: [0x01,0x4c]
+# CHECK-EL: addiusp 1028 # encoding: [0x03,0x4c]
# CHECK-EL: addiusp -16 # encoding: [0xf9,0x4f]
# CHECK-EL: mfhi $9 # encoding: [0x09,0x46]
# CHECK-EL: mflo $9 # encoding: [0x49,0x46]
@@ -71,6 +75,10 @@
# CHECK-EB: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
# CHECK-EB: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
# CHECK-EB: addius5 $7, -2 # encoding: [0x4c,0xfc]
+# CHECK-EB: addiusp -1028 # encoding: [0x4f,0xff]
+# CHECK-EB: addiusp -1032 # encoding: [0x4f,0xfd]
+# CHECK-EB: addiusp 1024 # encoding: [0x4c,0x01]
+# CHECK-EB: addiusp 1028 # encoding: [0x4c,0x03]
# CHECK-EB: addiusp -16 # encoding: [0x4f,0xf9]
# CHECK-EB: mfhi $9 # encoding: [0x46,0x09]
# CHECK-EB: mflo $9 # encoding: [0x46,0x49]
@@ -108,6 +116,10 @@
addiur2 $6, $7, -1
addiur2 $6, $7, 12
addius5 $7, -2
+ addiusp -1028
+ addiusp -1032
+ addiusp 1024
+ addiusp 1028
addiusp -16
mfhi $9
mflo $9
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