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authorElena Demikhovsky <elena.demikhovsky@intel.com>2015-05-17 08:08:06 +0000
committerElena Demikhovsky <elena.demikhovsky@intel.com>2015-05-17 08:08:06 +0000
commita8200603d4eeb50a2b771bb0b32edcb4c2c01d04 (patch)
treefa1144b308db9192b493249fe3b2162312c0c67e /llvm/lib
parent1d6a495d6df51a89c8493d18e1bf7384df757528 (diff)
downloadbcm5719-llvm-a8200603d4eeb50a2b771bb0b32edcb4c2c01d04.tar.gz
bcm5719-llvm-a8200603d4eeb50a2b771bb0b32edcb4c2c01d04.zip
AVX-512: fixed extended load to 512-bit register
llvm-svn: 237537
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 5ec719bbd8c..06528161e52 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -14022,8 +14022,8 @@ static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
"Can only lower sext loads with a single scalar load!");
unsigned loadRegZize = RegSz;
- if (Ext == ISD::SEXTLOAD && RegSz == 256)
- loadRegZize /= 2;
+ if (Ext == ISD::SEXTLOAD && RegSz >= 256)
+ loadRegZize = 128;
// Represent our vector as a sequence of elements which are the
// largest scalar that we can load.
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