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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-08-30 20:50:08 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-08-30 20:50:08 +0000 |
| commit | a609e2d5ceabe7f13d1093e26f9e5adbadaea9b0 (patch) | |
| tree | 266efdd3f9bec8c7b56e85d34eb5f588853112fe /llvm/lib | |
| parent | b077d3fef2278beb8f9652d55999f358f00256f1 (diff) | |
| download | bcm5719-llvm-a609e2d5ceabe7f13d1093e26f9e5adbadaea9b0.tar.gz bcm5719-llvm-a609e2d5ceabe7f13d1093e26f9e5adbadaea9b0.zip | |
AMDGPU: Relax SGPR asm constraint register class
s should be SReg_32 to be as general as possible. This can avoid a copy
from m0.
llvm-svn: 280154
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 28d9322a471..b79bdeadef3 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3751,7 +3751,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, default: return std::make_pair(0U, nullptr); case 32: - return std::make_pair(0U, &AMDGPU::SGPR_32RegClass); + return std::make_pair(0U, &AMDGPU::SReg_32RegClass); case 64: return std::make_pair(0U, &AMDGPU::SGPR_64RegClass); case 128: |
