diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/inline-constraints.ll | 10 |
2 files changed, 11 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 28d9322a471..b79bdeadef3 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3751,7 +3751,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, default: return std::make_pair(0U, nullptr); case 32: - return std::make_pair(0U, &AMDGPU::SGPR_32RegClass); + return std::make_pair(0U, &AMDGPU::SReg_32RegClass); case 64: return std::make_pair(0U, &AMDGPU::SGPR_64RegClass); case 128: diff --git a/llvm/test/CodeGen/AMDGPU/inline-constraints.ll b/llvm/test/CodeGen/AMDGPU/inline-constraints.ll index 78868710c6a..7282e89e85b 100644 --- a/llvm/test/CodeGen/AMDGPU/inline-constraints.ll +++ b/llvm/test/CodeGen/AMDGPU/inline-constraints.ll @@ -21,3 +21,13 @@ entry: %s256 = tail call <8 x i32> asm sideeffect "s_load_dwordx8 $0, $1", "=s,s"(i32 addrspace(1)* %ptr) ret void } + +; GCN-LABEL: {{^}}inline_sreg_constraint_m0: +; GCN: s_mov_b32 m0, -1 +; GCN-NOT: s_mov_b32 s{{[0-9]+}}, m0 +; GCN: ; use m0 +define void @inline_sreg_constraint_m0(i32 addrspace(1)* %ptr) { + %m0 = tail call i32 asm sideeffect "s_mov_b32 m0, -1", "={M0}"() + tail call void asm sideeffect "; use $0", "s"(i32 %m0) + ret void +} |
