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| author | Chris Lattner <sabre@nondot.org> | 2004-08-21 20:13:09 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2004-08-21 20:13:09 +0000 |
| commit | a440d5b081d374177ef49ea105143f780b8149e6 (patch) | |
| tree | 25da64c258e5ecfb2b6cb5f31d75199896a78387 /llvm/lib | |
| parent | b7ddc73b45ecb19829dcf584d7b4efc400d9cdf1 (diff) | |
| download | bcm5719-llvm-a440d5b081d374177ef49ea105143f780b8149e6.tar.gz bcm5719-llvm-a440d5b081d374177ef49ea105143f780b8149e6.zip | |
Convert regclass alignment from bytes to bites
llvm-svn: 15972
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td b/llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td index b59edaea20d..bea8f033db0 100644 --- a/llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td +++ b/llvm/lib/Target/SparcV9/SparcV9RegisterInfo.td @@ -35,7 +35,7 @@ let Namespace = "SparcV9" in { // FIXME: the register order should be defined in terms of the preferred // allocation order... // -def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7, +def IntRegs : RegisterClass<i64, 64, [G0, G1, G2, G3, G4, G5, G6, G7, O0, O1, O2, O3, O4, O5, O6, O7, L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, I6, I7]>; |
