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| author | Chris Lattner <sabre@nondot.org> | 2004-08-21 20:09:46 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2004-08-21 20:09:46 +0000 |
| commit | b7ddc73b45ecb19829dcf584d7b4efc400d9cdf1 (patch) | |
| tree | b06017d5d822639c2280c0519f10837230b32272 /llvm/lib | |
| parent | 36ba4bb0427614caf2ac47c72247844f4a8dbda6 (diff) | |
| download | bcm5719-llvm-b7ddc73b45ecb19829dcf584d7b4efc400d9cdf1.tar.gz bcm5719-llvm-b7ddc73b45ecb19829dcf584d7b4efc400d9cdf1.zip | |
Convert bytes to bits in alignment
llvm-svn: 15971
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td b/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td index ccbdb2054ac..9c3d355c35a 100644 --- a/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td +++ b/llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td @@ -71,7 +71,7 @@ let Namespace = "V8" in { // FIXME: the register order should be defined in terms of the preferred // allocation order... // -def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7, +def IntRegs : RegisterClass<i32, 64, [L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, G1, G2, G3, G4, G5, G6, G7, O0, O1, O2, O3, O4, O5, O7, @@ -84,11 +84,11 @@ def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7, }]; } -def FPRegs : RegisterClass<f32, 4, [F0, F1, F2, F3, F4, F5, F6, F7, F8, +def FPRegs : RegisterClass<f32, 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>; -def DFPRegs : RegisterClass<f64, 8, [D0, D1, D2, D3, D4, D5, D6, D7, +def DFPRegs : RegisterClass<f64, 64, [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15]>; // Tell the register file generator that the double-fp pseudo-registers |
