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| author | Craig Topper <craig.topper@intel.com> | 2019-09-20 06:00:35 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-20 06:00:35 +0000 |
| commit | a34f13f2bab3bb3a25ce999defb616558cbc3f4f (patch) | |
| tree | 1ed35cdb2ab01d751a6bb8aa8c14ebc6830bcb35 /llvm/lib | |
| parent | c768ad94b7f0be9feb86dd5cfcdb4158a5a28dd7 (diff) | |
| download | bcm5719-llvm-a34f13f2bab3bb3a25ce999defb616558cbc3f4f.tar.gz bcm5719-llvm-a34f13f2bab3bb3a25ce999defb616558cbc3f4f.zip | |
[X86] Use timm in MMX pinsrw/pextrw isel patterns. Add missing test cases.
This fixes an isel failure after r372338.
llvm-svn: 372371
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index 08104c8bcc6..93b318403f7 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -535,7 +535,7 @@ def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2), "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1, - imm:$src2))]>, + timm:$src2))]>, Sched<[WriteVecExtract]>; let Constraints = "$src1 = $dst" in { let Predicates = [HasMMX, HasSSE1] in { @@ -544,7 +544,7 @@ let Predicates = [HasMMX, HasSSE1] in { (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3), "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, - GR32orGR64:$src2, imm:$src3))]>, + GR32orGR64:$src2, timm:$src3))]>, Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>; def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem, @@ -553,7 +553,7 @@ let Predicates = [HasMMX, HasSSE1] in { "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, (i32 (anyext (loadi16 addr:$src2))), - imm:$src3))]>, + timm:$src3))]>, Sched<[WriteVecInsert.Folded, WriteVecInsert.ReadAfterFold]>; } } |
