diff options
| author | Craig Topper <craig.topper@intel.com> | 2019-09-20 06:00:35 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-20 06:00:35 +0000 |
| commit | a34f13f2bab3bb3a25ce999defb616558cbc3f4f (patch) | |
| tree | 1ed35cdb2ab01d751a6bb8aa8c14ebc6830bcb35 | |
| parent | c768ad94b7f0be9feb86dd5cfcdb4158a5a28dd7 (diff) | |
| download | bcm5719-llvm-a34f13f2bab3bb3a25ce999defb616558cbc3f4f.tar.gz bcm5719-llvm-a34f13f2bab3bb3a25ce999defb616558cbc3f4f.zip | |
[X86] Use timm in MMX pinsrw/pextrw isel patterns. Add missing test cases.
This fixes an isel failure after r372338.
llvm-svn: 372371
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/mmx-intrinsics.ll | 65 |
2 files changed, 68 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index 08104c8bcc6..93b318403f7 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -535,7 +535,7 @@ def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2), "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1, - imm:$src2))]>, + timm:$src2))]>, Sched<[WriteVecExtract]>; let Constraints = "$src1 = $dst" in { let Predicates = [HasMMX, HasSSE1] in { @@ -544,7 +544,7 @@ let Predicates = [HasMMX, HasSSE1] in { (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3), "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, - GR32orGR64:$src2, imm:$src3))]>, + GR32orGR64:$src2, timm:$src3))]>, Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>; def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem, @@ -553,7 +553,7 @@ let Predicates = [HasMMX, HasSSE1] in { "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, (i32 (anyext (loadi16 addr:$src2))), - imm:$src3))]>, + timm:$src3))]>, Sched<[WriteVecInsert.Folded, WriteVecInsert.ReadAfterFold]>; } } diff --git a/llvm/test/CodeGen/X86/mmx-intrinsics.ll b/llvm/test/CodeGen/X86/mmx-intrinsics.ll index b9655830619..48d4ad0490f 100644 --- a/llvm/test/CodeGen/X86/mmx-intrinsics.ll +++ b/llvm/test/CodeGen/X86/mmx-intrinsics.ll @@ -1453,3 +1453,68 @@ define void @test90() { } declare void @llvm.x86.mmx.emms() + +define <1 x i64> @test_mm_insert_pi16(<1 x i64> %a.coerce, i32 %d) nounwind { +; X86-LABEL: test_mm_insert_pi16: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pinsrw $2, 16(%ebp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test_mm_insert_pi16: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: pinsrw $2, %esi, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq +entry: + %0 = bitcast <1 x i64> %a.coerce to x86_mmx + %1 = tail call x86_mmx @llvm.x86.mmx.pinsr.w(x86_mmx %0, i32 %d, i32 2) + %2 = bitcast x86_mmx %1 to <1 x i64> + ret <1 x i64> %2 +} + +declare x86_mmx @llvm.x86.mmx.pinsr.w(x86_mmx, i32, i32 immarg) + +define i32 @test_mm_extract_pi16(<1 x i64> %a.coerce) nounwind { +; X86-LABEL: test_mm_extract_pi16: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: movq (%esp), %mm0 +; X86-NEXT: pextrw $2, %mm0, %eax +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test_mm_extract_pi16: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: pextrw $2, %mm0, %eax +; X64-NEXT: retq +entry: + %0 = bitcast <1 x i64> %a.coerce to x86_mmx + %1 = tail call i32 @llvm.x86.mmx.pextr.w(x86_mmx %0, i32 2) + ret i32 %1 +} + +declare i32 @llvm.x86.mmx.pextr.w(x86_mmx, i32 immarg) |
