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| author | Chris Lattner <sabre@nondot.org> | 2005-04-30 04:26:06 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-04-30 04:26:06 +0000 |
| commit | 9c6bbafc15aaea7251f4b99b721587bfff45d0e7 (patch) | |
| tree | 892d498c522b71261cb0b1613c4d1502d65b8364 /llvm/lib | |
| parent | db68d39a01e48fafcb07ee82ac0a8a4c5f2e6a65 (diff) | |
| download | bcm5719-llvm-9c6bbafc15aaea7251f4b99b721587bfff45d0e7.tar.gz bcm5719-llvm-9c6bbafc15aaea7251f4b99b721587bfff45d0e7.zip | |
This target doesn't support the FSIN/FCOS/FSQRT nodes yet
llvm-svn: 21633
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/IA64/IA64ISelPattern.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp | 8 |
3 files changed, 25 insertions, 1 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index e2e863deac0..31b6fd6d013 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -84,8 +84,16 @@ namespace { setOperationAction(ISD::MEMSET , MVT::Other, Expand); setOperationAction(ISD::MEMCPY , MVT::Other, Expand); + // We don't support sin/cos/sqrt + setOperationAction(ISD::FSIN , MVT::f64, Expand); + setOperationAction(ISD::FCOS , MVT::f64, Expand); + setOperationAction(ISD::FSQRT, MVT::f64, Expand); + setOperationAction(ISD::FSIN , MVT::f32, Expand); + setOperationAction(ISD::FCOS , MVT::f32, Expand); + setOperationAction(ISD::FSQRT, MVT::f32, Expand); + //Doesn't work yet - setOperationAction(ISD::SETCC , MVT::f32, Promote); + setOperationAction(ISD::SETCC, MVT::f32, Promote); computeRegisterProperties(); diff --git a/llvm/lib/Target/IA64/IA64ISelPattern.cpp b/llvm/lib/Target/IA64/IA64ISelPattern.cpp index c3675a0da0a..1fe9026ed0f 100644 --- a/llvm/lib/Target/IA64/IA64ISelPattern.cpp +++ b/llvm/lib/Target/IA64/IA64ISelPattern.cpp @@ -81,6 +81,14 @@ namespace { setOperationAction(ISD::MEMSET , MVT::Other, Expand); setOperationAction(ISD::MEMCPY , MVT::Other, Expand); + // We don't support sin/cos/sqrt + setOperationAction(ISD::FSIN , MVT::f64, Expand); + setOperationAction(ISD::FCOS , MVT::f64, Expand); + setOperationAction(ISD::FSQRT, MVT::f64, Expand); + setOperationAction(ISD::FSIN , MVT::f32, Expand); + setOperationAction(ISD::FCOS , MVT::f32, Expand); + setOperationAction(ISD::FSQRT, MVT::f32, Expand); + computeRegisterProperties(); addLegalFPImmediate(+0.0); diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp index 40a2610f2cd..a5732f05767 100644 --- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp +++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp @@ -61,6 +61,14 @@ namespace { setOperationAction(ISD::SREM, MVT::i32, Expand); setOperationAction(ISD::UREM, MVT::i32, Expand); + // We don't support sin/cos/sqrt + setOperationAction(ISD::FSIN , MVT::f64, Expand); + setOperationAction(ISD::FCOS , MVT::f64, Expand); + setOperationAction(ISD::FSQRT, MVT::f64, Expand); + setOperationAction(ISD::FSIN , MVT::f32, Expand); + setOperationAction(ISD::FCOS , MVT::f32, Expand); + setOperationAction(ISD::FSQRT, MVT::f32, Expand); + setSetCCResultContents(ZeroOrOneSetCCResult); addLegalFPImmediate(+0.0); // Necessary for FSEL addLegalFPImmediate(-0.0); // |
