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| author | Oliver Stannard <oliver.stannard@arm.com> | 2014-11-11 17:36:01 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2014-11-11 17:36:01 +0000 |
| commit | 8c2c67e63c016b6708897eb6ca5816af416148bd (patch) | |
| tree | 31a3fa2ccc13a91a89448cbca711fccfae7f9587 /llvm/lib | |
| parent | 1ecb68d5ce702fcebef4243a9a49c65f6d5ee797 (diff) | |
| download | bcm5719-llvm-8c2c67e63c016b6708897eb6ca5816af416148bd.tar.gz bcm5719-llvm-8c2c67e63c016b6708897eb6ca5816af416148bd.zip | |
LLVM incorrectly folds xor into select
LLVM replaces the SelectionDAG pattern (xor (set_cc cc x y) 1) with
(set_cc !cc x y), which is only correct when the xor has type i1.
Instead, we should check that the constant operand to the xor is all
ones.
llvm-svn: 221693
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 33b2527287e..530ced6e532 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3826,7 +3826,8 @@ SDValue DAGCombiner::visitXOR(SDNode *N) { return RXOR; // fold !(x cc y) -> (x !cc y) - if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { + if (N1C && N1C->getAPIntValue().isAllOnesValue() && + isSetCCEquivalent(N0, LHS, RHS, CC)) { bool isInt = LHS.getValueType().isInteger(); ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), isInt); |
