diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/select_xform.ll | 17 |
2 files changed, 19 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 33b2527287e..530ced6e532 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -3826,7 +3826,8 @@ SDValue DAGCombiner::visitXOR(SDNode *N) { return RXOR; // fold !(x cc y) -> (x !cc y) - if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { + if (N1C && N1C->getAPIntValue().isAllOnesValue() && + isSetCCEquivalent(N0, LHS, RHS, CC)) { bool isInt = LHS.getValueType().isInteger(); ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), isInt); diff --git a/llvm/test/CodeGen/ARM/select_xform.ll b/llvm/test/CodeGen/ARM/select_xform.ll index e13504a42a1..850d4cd73d7 100644 --- a/llvm/test/CodeGen/ARM/select_xform.ll +++ b/llvm/test/CodeGen/ARM/select_xform.ll @@ -222,3 +222,20 @@ entry: %add = add i32 %conv, %c ret i32 %add } + +; Do not fold the xor into the select +define i32 @t15(i32 %p1, i32 %p2, i32 %p3) { +entry: +; ARM: cmp r0, #8 +; ARM: mov{{(le|gt)}} [[REG:r[0-9]+]], {{r[0-9]+}} +; ARM: eor r0, [[REG]], #1 + +; T2: cmp r0, #8 +; T2: it [[CC:(le|gt)]] +; T2: mov[[CC]] [[REG:r[0-9]+]], {{r[0-9]+}} +; T2: eor r0, [[REG:r[0-9]+]], #1 + %cmp = icmp sgt i32 %p1, 8 + %a = select i1 %cmp, i32 %p2, i32 %p3 + %xor = xor i32 %a, 1 + ret i32 %xor +} |
