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| author | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-27 12:26:24 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-07-27 12:26:24 +0000 |
| commit | 71929e7cad088113598afb36e818138b8ee52ef1 (patch) | |
| tree | 1ec25eac9213803988a3e9d6898af4282f759b90 /llvm/lib | |
| parent | 5fed24a39698466952504850e8fd7703e17ce679 (diff) | |
| download | bcm5719-llvm-71929e7cad088113598afb36e818138b8ee52ef1.tar.gz bcm5719-llvm-71929e7cad088113598afb36e818138b8ee52ef1.zip | |
[AArch64][SVE] Asm: Support for FRECPE and FRSQRTE.
Support for floating-point instructions for reciprocal
estimate (FRECPE) and reciprocal square root estimate (FRSQRTE).
llvm-svn: 338120
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 27 |
2 files changed, 30 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index d40f7d8046b..2a8dde28f78 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -102,6 +102,9 @@ let Predicates = [HasSVE] in { defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd">; defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd">; + defm FRECPE_ZZ : sve_fp_2op_u_zd<0b110, "frecpe">; + defm FRSQRTE_ZZ : sve_fp_2op_u_zd<0b111, "frsqrte">; + defm FADD_ZPmI : sve_fp_2op_i_p_zds<0b000, "fadd", sve_fpimm_half_one>; defm FSUB_ZPmI : sve_fp_2op_i_p_zds<0b001, "fsub", sve_fpimm_half_one>; defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index c334b1f8df7..cb2cb12788f 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -1432,6 +1432,33 @@ multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm> { } //===----------------------------------------------------------------------===// +// SVE Floating Point Unary Operations - Unpredicated Group +//===----------------------------------------------------------------------===// + +class sve_fp_2op_u_zd<bits<2> sz, bits<3> opc, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$Zn), + asm, "\t$Zd, $Zn", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zn; + let Inst{31-24} = 0b01100101; + let Inst{23-22} = sz; + let Inst{21-19} = 0b001; + let Inst{18-16} = opc; + let Inst{15-10} = 0b001100; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve_fp_2op_u_zd<bits<3> opc, string asm> { + def _H : sve_fp_2op_u_zd<0b01, opc, asm, ZPR16>; + def _S : sve_fp_2op_u_zd<0b10, opc, asm, ZPR32>; + def _D : sve_fp_2op_u_zd<0b11, opc, asm, ZPR64>; +} + +//===----------------------------------------------------------------------===// // SVE Integer Arithmetic - Binary Predicated Group //===----------------------------------------------------------------------===// |
