[AArch64][SVE] Asm: Support for FRECPE and FRSQRTE.

Support for floating-point instructions for reciprocal
estimate (FRECPE) and reciprocal square root estimate (FRSQRTE).

llvm-svn: 338120

6 files changed, 94 insertions, 0 deletions

diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index d40f7d8046b..2a8dde28f78 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -102,6 +102,9 @@ let Predicates = [HasSVE] in {
   defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd">;
   defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd">;
 
+  defm FRECPE_ZZ  : sve_fp_2op_u_zd<0b110, "frecpe">;
+  defm FRSQRTE_ZZ : sve_fp_2op_u_zd<0b111, "frsqrte">;
+
   defm FADD_ZPmI    : sve_fp_2op_i_p_zds<0b000, "fadd", sve_fpimm_half_one>;
   defm FSUB_ZPmI    : sve_fp_2op_i_p_zds<0b001, "fsub", sve_fpimm_half_one>;
   defm FMUL_ZPmI    : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index c334b1f8df7..cb2cb12788f 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -1432,6 +1432,33 @@ multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm> {
 }
  
 //===----------------------------------------------------------------------===//
+// SVE Floating Point Unary Operations - Unpredicated Group
+//===----------------------------------------------------------------------===//
+
+class sve_fp_2op_u_zd<bits<2> sz, bits<3> opc, string asm,
+                      ZPRRegOp zprty>
+: I<(outs zprty:$Zd), (ins zprty:$Zn),
+  asm, "\t$Zd, $Zn",
+  "",
+  []>, Sched<[]> {
+  bits<5> Zd;
+  bits<5> Zn;
+  let Inst{31-24} = 0b01100101;
+  let Inst{23-22} = sz;
+  let Inst{21-19} = 0b001;
+  let Inst{18-16} = opc;
+  let Inst{15-10} = 0b001100;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zd;
+}
+
+multiclass sve_fp_2op_u_zd<bits<3> opc, string asm> {
+  def _H : sve_fp_2op_u_zd<0b01, opc, asm, ZPR16>;
+  def _S : sve_fp_2op_u_zd<0b10, opc, asm, ZPR32>;
+  def _D : sve_fp_2op_u_zd<0b11, opc, asm, ZPR64>;
+}
+
+//===----------------------------------------------------------------------===//
 // SVE Integer Arithmetic - Binary Predicated Group
 //===----------------------------------------------------------------------===//
 
diff --git a/llvm/test/MC/AArch64/SVE/frecpe-diagnostics.s b/llvm/test/MC/AArch64/SVE/frecpe-diagnostics.s
new file mode 100644
index 00000000000..80467f26f5a
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/frecpe-diagnostics.s
@@ -0,0 +1,6 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+frecpe    z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: frecpe    z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/frecpe.s b/llvm/test/MC/AArch64/SVE/frecpe.s
new file mode 100644
index 00000000000..3b559d951f6
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/frecpe.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+frecpe   z0.h, z31.h
+// CHECK-INST: frecpe	z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x33,0x4e,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 33 4e 65 <unknown>
+
+frecpe   z0.s, z31.s
+// CHECK-INST: frecpe	z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x33,0x8e,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 33 8e 65 <unknown>
+
+frecpe   z0.d, z31.d
+// CHECK-INST: frecpe	z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x33,0xce,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 33 ce 65 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/frsqrte-diagnostics.s b/llvm/test/MC/AArch64/SVE/frsqrte-diagnostics.s
new file mode 100644
index 00000000000..b7325e164aa
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/frsqrte-diagnostics.s
@@ -0,0 +1,6 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+frsqrte   z0.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: frsqrte   z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/frsqrte.s b/llvm/test/MC/AArch64/SVE/frsqrte.s
new file mode 100644
index 00000000000..e0fa387b665
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/frsqrte.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+frsqrte  z0.h, z31.h
+// CHECK-INST: frsqrte	z0.h, z31.h
+// CHECK-ENCODING: [0xe0,0x33,0x4f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 33 4f 65 <unknown>
+
+frsqrte  z0.s, z31.s
+// CHECK-INST: frsqrte	z0.s, z31.s
+// CHECK-ENCODING: [0xe0,0x33,0x8f,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 33 8f 65 <unknown>
+
+frsqrte  z0.d, z31.d
+// CHECK-INST: frsqrte	z0.d, z31.d
+// CHECK-ENCODING: [0xe0,0x33,0xcf,0x65]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 33 cf 65 <unknown>