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| author | Tim Northover <tnorthover@apple.com> | 2018-04-10 11:04:29 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2018-04-10 11:04:29 +0000 |
| commit | 6a1c51bf6b5ac7ebba570206f61bdd56cfae728c (patch) | |
| tree | 9b8d158ea670bdbf018650c47300a1939a6565ab /llvm/lib | |
| parent | 486358c153f13dd06fbe2c645ce497b39652358f (diff) | |
| download | bcm5719-llvm-6a1c51bf6b5ac7ebba570206f61bdd56cfae728c.tar.gz bcm5719-llvm-6a1c51bf6b5ac7ebba570206f61bdd56cfae728c.zip | |
AArch64: diagnose unpredictable store-exclusive instructions
Much like any written register in load/store instructions, the status register
is not allowed to overlap with any others. So diagnose it like we already do
with the other cases.
llvm-svn: 329687
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index f2e4d79daba..1e2255c8a04 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3435,7 +3435,39 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, "is also a source"); break; } + case AArch64::STXRB: + case AArch64::STXRH: + case AArch64::STXRW: + case AArch64::STXRX: + case AArch64::STLXRB: + case AArch64::STLXRH: + case AArch64::STLXRW: + case AArch64::STLXRX: { + unsigned Rs = Inst.getOperand(0).getReg(); + unsigned Rt = Inst.getOperand(1).getReg(); + unsigned Rn = Inst.getOperand(2).getReg(); + if (RI->isSubRegisterEq(Rt, Rs) || + (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP)) + return Error(Loc[0], + "unpredictable STXR instruction, status is also a source"); + break; } + case AArch64::STXPW: + case AArch64::STXPX: + case AArch64::STLXPW: + case AArch64::STLXPX: { + unsigned Rs = Inst.getOperand(0).getReg(); + unsigned Rt1 = Inst.getOperand(1).getReg(); + unsigned Rt2 = Inst.getOperand(2).getReg(); + unsigned Rn = Inst.getOperand(3).getReg(); + if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) || + (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP)) + return Error(Loc[0], + "unpredictable STXP instruction, status is also a source"); + break; + } + } + // Now check immediate ranges. Separate from the above as there is overlap // in the instructions being checked and this keeps the nested conditionals |
