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-rw-r--r--llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp32
-rw-r--r--llvm/test/MC/AArch64/arm64-diags.s61
-rw-r--r--llvm/test/MC/AArch64/arm64-memory.s16
3 files changed, 101 insertions, 8 deletions
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index f2e4d79daba..1e2255c8a04 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3435,7 +3435,39 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst,
"is also a source");
break;
}
+ case AArch64::STXRB:
+ case AArch64::STXRH:
+ case AArch64::STXRW:
+ case AArch64::STXRX:
+ case AArch64::STLXRB:
+ case AArch64::STLXRH:
+ case AArch64::STLXRW:
+ case AArch64::STLXRX: {
+ unsigned Rs = Inst.getOperand(0).getReg();
+ unsigned Rt = Inst.getOperand(1).getReg();
+ unsigned Rn = Inst.getOperand(2).getReg();
+ if (RI->isSubRegisterEq(Rt, Rs) ||
+ (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
+ return Error(Loc[0],
+ "unpredictable STXR instruction, status is also a source");
+ break;
}
+ case AArch64::STXPW:
+ case AArch64::STXPX:
+ case AArch64::STLXPW:
+ case AArch64::STLXPX: {
+ unsigned Rs = Inst.getOperand(0).getReg();
+ unsigned Rt1 = Inst.getOperand(1).getReg();
+ unsigned Rt2 = Inst.getOperand(2).getReg();
+ unsigned Rn = Inst.getOperand(3).getReg();
+ if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) ||
+ (RI->isSubRegisterEq(Rn, Rs) && Rn != AArch64::SP))
+ return Error(Loc[0],
+ "unpredictable STXP instruction, status is also a source");
+ break;
+ }
+ }
+
// Now check immediate ranges. Separate from the above as there is overlap
// in the instructions being checked and this keeps the nested conditionals
diff --git a/llvm/test/MC/AArch64/arm64-diags.s b/llvm/test/MC/AArch64/arm64-diags.s
index 3510193a71f..591ff64eb33 100644
--- a/llvm/test/MC/AArch64/arm64-diags.s
+++ b/llvm/test/MC/AArch64/arm64-diags.s
@@ -246,6 +246,67 @@ ldr q1, [x3, w3, sxtw #1]
; CHECK-ERRORS: str w2, [x2, #8]!
; CHECK-ERRORS: ^
+; Store exclusive instructions are unpredictable if the status register clashes
+; with anything.
+ stlxrb w1, w1, [x5]
+ stxrb w3, w5, [x3]
+ stxrh w7, w9, [x7]
+ stlxrh wzr, wzr, [x13]
+ stxr w9, w9, [x12]
+ stlxr w22, x1, [x22]
+ stxr w4, x4, [x9]
+ stlxr w5, x0, [x5]
+; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
+; CHECK-ERRORS: stlxrb w1, w1, [x5]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
+; CHECK-ERRORS: stxrb w3, w5, [x3]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
+; CHECK-ERRORS: stxrh w7, w9, [x7]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
+; CHECK-ERRORS: stlxrh wzr, wzr, [x13]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
+; CHECK-ERRORS: stxr w9, w9, [x12]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
+; CHECK-ERRORS: stlxr w22, x1, [x22]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
+; CHECK-ERRORS: stxr w4, x4, [x9]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
+; CHECK-ERRORS: stlxr w5, x0, [x5]
+; CHECK-ERRORS: ^
+
+ stxp w0, w0, w1, [x3]
+ stxp w0, w1, w0, [x5]
+ stxp w10, w4, w5, [x10]
+ stxp wzr, xzr, x4, [x5]
+ stxp w3, x5, x3, [sp]
+ stxp w25, x4, x2, [x25]
+; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
+; CHECK-ERRORS: stxp w0, w0, w1, [x3]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
+; CHECK-ERRORS: stxp w0, w1, w0, [x5]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
+; CHECK-ERRORS: stxp w10, w4, w5, [x10]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
+; CHECK-ERRORS: stxp wzr, xzr, x4, [x5]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
+; CHECK-ERRORS: stxp w3, x5, x3, [sp]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
+; CHECK-ERRORS: stxp w25, x4, x2, [x25]
+; CHECK-ERRORS: ^
+
+
; The validity checking for shifted-immediate operands. rdar://13174476
; Where the immediate is out of range.
add w1, w2, w3, lsr #75
diff --git a/llvm/test/MC/AArch64/arm64-memory.s b/llvm/test/MC/AArch64/arm64-memory.s
index 579859660f9..fd4630d4f9c 100644
--- a/llvm/test/MC/AArch64/arm64-memory.s
+++ b/llvm/test/MC/AArch64/arm64-memory.s
@@ -469,15 +469,15 @@ foo:
stxr w1, w4, [x3]
stxrb w1, w4, [x3]
stxrh w1, w4, [x3]
- stxp w1, x2, x6, [x1]
- stxp w1, w2, w6, [x1]
+ stxp w1, x2, x6, [x7]
+ stxp w1, w2, w6, [x9]
; CHECK: stxr w1, x4, [x3] ; encoding: [0x64,0x7c,0x01,0xc8]
; CHECK: stxr w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x88]
; CHECK: stxrb w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x08]
; CHECK: stxrh w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x48]
-; CHECK: stxp w1, x2, x6, [x1] ; encoding: [0x22,0x18,0x21,0xc8]
-; CHECK: stxp w1, w2, w6, [x1] ; encoding: [0x22,0x18,0x21,0x88]
+; CHECK: stxp w1, x2, x6, [x7] ; encoding: [0xe2,0x18,0x21,0xc8]
+; CHECK: stxp w1, w2, w6, [x9] ; encoding: [0x22,0x19,0x21,0x88]
;-----------------------------------------------------------------------------
; Load-acquire/Store-release non-exclusive
@@ -525,15 +525,15 @@ foo:
stlxr w8, w7, [x1]
stlxrb w8, w7, [x1]
stlxrh w8, w7, [x1]
- stlxp w1, x2, x6, [x1]
- stlxp w1, w2, w6, [x1]
+ stlxp w1, x2, x6, [x7]
+ stlxp w1, w2, w6, [x9]
; CHECK: stlxr w8, x7, [x1] ; encoding: [0x27,0xfc,0x08,0xc8]
; CHECK: stlxr w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x88]
; CHECK: stlxrb w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x08]
; CHECK: stlxrh w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x48]
-; CHECK: stlxp w1, x2, x6, [x1] ; encoding: [0x22,0x98,0x21,0xc8]
-; CHECK: stlxp w1, w2, w6, [x1] ; encoding: [0x22,0x98,0x21,0x88]
+; CHECK: stlxp w1, x2, x6, [x7] ; encoding: [0xe2,0x98,0x21,0xc8]
+; CHECK: stlxp w1, w2, w6, [x9] ; encoding: [0x22,0x99,0x21,0x88]
;-----------------------------------------------------------------------------
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