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| author | Tim Northover <tnorthover@apple.com> | 2016-03-10 23:02:21 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2016-03-10 23:02:21 +0000 |
| commit | 6092de50750e85b6866950884512ba281d431391 (patch) | |
| tree | 191ce722dd6e8f2cb09445b6e4a8a4630fee37ea /llvm/lib | |
| parent | 416ad130eab2047e64fa1be7ab5f60a6caad7cb9 (diff) | |
| download | bcm5719-llvm-6092de50750e85b6866950884512ba281d431391.tar.gz bcm5719-llvm-6092de50750e85b6866950884512ba281d431391.zip | |
AArch64: only try to use scaled fcvt ops on legal vector types.
Before we ended up calling getSimpleVectorType on a <3 x float>, which
asserted.
llvm-svn: 263169
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index f5f2043fd68..ecb8eb19c18 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -7687,7 +7687,8 @@ static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG, return SDValue(); SDValue Op = N->getOperand(0); - if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL) + if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() || + Op.getOpcode() != ISD::FMUL) return SDValue(); SDValue ConstVec = Op->getOperand(1); |
