diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/fcvt_combine.ll | 8 |
2 files changed, 10 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index f5f2043fd68..ecb8eb19c18 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -7687,7 +7687,8 @@ static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG, return SDValue(); SDValue Op = N->getOperand(0); - if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL) + if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() || + Op.getOpcode() != ISD::FMUL) return SDValue(); SDValue ConstVec = Op->getOperand(1); diff --git a/llvm/test/CodeGen/AArch64/fcvt_combine.ll b/llvm/test/CodeGen/AArch64/fcvt_combine.ll index 093ce4a4cd8..5644fa28533 100644 --- a/llvm/test/CodeGen/AArch64/fcvt_combine.ll +++ b/llvm/test/CodeGen/AArch64/fcvt_combine.ll @@ -152,3 +152,11 @@ define <2 x i32> @test14(<2 x float> %f) { %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> ret <2 x i32> %vcvt.i } + +; CHECK-LABEL: test_illegal_fp_to_int: +; CHECK: fcvtzs.4s v0, v0, #2 +define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) { + %scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0> + %val = fptosi <3 x float> %scale to <3 x i32> + ret <3 x i32> %val +} |
