diff options
| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-09-15 16:17:27 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-09-15 16:17:27 +0000 |
| commit | 50f17235dd45e7023dda46cba0ea15ce1ef3f6f0 (patch) | |
| tree | 71b2f96146d2527596bd82be6357fe5c435369e0 /llvm/lib | |
| parent | e9434e80d141d754cdf7efc6cf3b7ca311ca2750 (diff) | |
| download | bcm5719-llvm-50f17235dd45e7023dda46cba0ea15ce1ef3f6f0.tar.gz bcm5719-llvm-50f17235dd45e7023dda46cba0ea15ce1ef3f6f0.zip | |
Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.
Eric has replied and has demanded the patch be reverted.
llvm-svn: 247702
Diffstat (limited to 'llvm/lib')
100 files changed, 407 insertions, 754 deletions
diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp index e2c5ce0e7f3..37299eb664c 100644 --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -170,7 +170,7 @@ bool LLVMTargetMachine::addPassesToEmitFile( switch (FileType) { case CGFT_AssemblyFile: { MCInstPrinter *InstPrinter = getTarget().createMCInstPrinter( - getTargetTuple(), MAI.getAssemblerDialect(), MAI, MII, MRI); + getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI); // Create a code emitter if asked to show the encoding. MCCodeEmitter *MCE = nullptr; @@ -199,7 +199,7 @@ bool LLVMTargetMachine::addPassesToEmitFile( // Don't waste memory on names of temp labels. Context->setUseNamesOnTempLabels(false); - TargetTuple T(Triple(getTargetTriple().str())); + Triple T(getTargetTriple().str()); AsmStreamer.reset(getTarget().createMCObjectStreamer( T, *Context, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll, /*DWARFMustBeAtTheEnd*/ true)); @@ -250,10 +250,10 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx, if (!MCE || !MAB) return true; - const TargetTuple &TT = getTargetTuple(); + const Triple &T = getTargetTriple(); const MCSubtargetInfo &STI = *getMCSubtargetInfo(); std::unique_ptr<MCStreamer> AsmStreamer(getTarget().createMCObjectStreamer( - TT, *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll, + T, *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll, /*DWARFMustBeAtTheEnd*/ true)); // Create the AsmPrinter, which takes ownership of AsmStreamer if successful. diff --git a/llvm/lib/MC/MCDisassembler/Disassembler.cpp b/llvm/lib/MC/MCDisassembler/Disassembler.cpp index 3d0216218c9..82063fb7469 100644 --- a/llvm/lib/MC/MCDisassembler/Disassembler.cpp +++ b/llvm/lib/MC/MCDisassembler/Disassembler.cpp @@ -83,7 +83,7 @@ LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU, // Set up the instruction printer. int AsmPrinterVariant = MAI->getAssemblerDialect(); MCInstPrinter *IP = TheTarget->createMCInstPrinter( - TargetTuple(Triple(TT)), AsmPrinterVariant, *MAI, *MII, *MRI); + Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI); if (!IP) return nullptr; @@ -310,8 +310,7 @@ int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){ int AsmPrinterVariant = MAI->getAssemblerDialect(); AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0; MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter( - TargetTuple(Triple(DC->getTripleName())), AsmPrinterVariant, *MAI, - *MII, *MRI); + Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI); if (IP) { DC->setIP(IP); DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant); diff --git a/llvm/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp b/llvm/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp index 4c0bf318f28..5fc2ca44f5d 100644 --- a/llvm/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp +++ b/llvm/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp @@ -17,7 +17,7 @@ using namespace llvm; namespace llvm { -class TargetTuple; +class Triple; } // This function tries to add a symbolic operand in place of the immediate @@ -188,8 +188,7 @@ void MCExternalSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, } namespace llvm { -MCSymbolizer *createMCSymbolizer(const TargetTuple &TT, - LLVMOpInfoCallback GetOpInfo, +MCSymbolizer *createMCSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo) { diff --git a/llvm/lib/MC/MCDisassembler/MCRelocationInfo.cpp b/llvm/lib/MC/MCDisassembler/MCRelocationInfo.cpp index 27534fccf2c..43005e7c740 100644 --- a/llvm/lib/MC/MCDisassembler/MCRelocationInfo.cpp +++ b/llvm/lib/MC/MCDisassembler/MCRelocationInfo.cpp @@ -34,7 +34,7 @@ MCRelocationInfo::createExprForCAPIVariantKind(const MCExpr *SubExpr, return SubExpr; } -MCRelocationInfo *llvm::createMCRelocationInfo(const TargetTuple &TT, +MCRelocationInfo *llvm::createMCRelocationInfo(const Triple &TT, MCContext &Ctx) { return new MCRelocationInfo(Ctx); } diff --git a/llvm/lib/MC/MCSubtargetInfo.cpp b/llvm/lib/MC/MCSubtargetInfo.cpp index 5df168c40dd..9210cf544b1 100644 --- a/llvm/lib/MC/MCSubtargetInfo.cpp +++ b/llvm/lib/MC/MCSubtargetInfo.cpp @@ -9,7 +9,7 @@ #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/ADT/StringRef.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/raw_ostream.h" @@ -37,12 +37,12 @@ void MCSubtargetInfo::setDefaultFeatures(StringRef CPU) { } MCSubtargetInfo::MCSubtargetInfo( - const TargetTuple &TT, StringRef C, StringRef FS, + const Triple &TT, StringRef C, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) - : TheTargetTuple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD), + : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD), ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL), ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) { InitMCProcessorInfo(CPU, FS); diff --git a/llvm/lib/Support/CMakeLists.txt b/llvm/lib/Support/CMakeLists.txt index 0db4055f711..badfd99b673 100644 --- a/llvm/lib/Support/CMakeLists.txt +++ b/llvm/lib/Support/CMakeLists.txt @@ -88,7 +88,6 @@ add_llvm_library(LLVMSupport StringRef.cpp SystemUtils.cpp TargetParser.cpp - TargetTuple.cpp Timer.cpp ToolOutputFile.cpp Triple.cpp diff --git a/llvm/lib/Support/TargetTuple.cpp b/llvm/lib/Support/TargetTuple.cpp deleted file mode 100644 index 3db21f91785..00000000000 --- a/llvm/lib/Support/TargetTuple.cpp +++ /dev/null @@ -1,315 +0,0 @@ -//===--- TargetTuple.cpp - Target tuple class -----------------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/ADT/StringSwitch.h" -#include "llvm/ADT/TargetTuple.h" -#include "llvm/Support/TargetParser.h" - -using namespace llvm; - -// FIXME: These should be removed as soon as the Triple member is replaced. -static TargetTuple::ArchType -convertTripleArchToTupleArch(Triple::ArchType Arch) { - switch (Arch) { - case Triple::UnknownArch: - return TargetTuple::UnknownArch; - case Triple::arm: - return TargetTuple::arm; - case Triple::armeb: - return TargetTuple::armeb; - case Triple::aarch64: - return TargetTuple::aarch64; - case Triple::aarch64_be: - return TargetTuple::aarch64_be; - case Triple::bpfel: - return TargetTuple::bpfel; - case Triple::bpfeb: - return TargetTuple::bpfeb; - case Triple::hexagon: - return TargetTuple::hexagon; - case Triple::mips: - return TargetTuple::mips; - case Triple::mipsel: - return TargetTuple::mipsel; - case Triple::mips64: - return TargetTuple::mips64; - case Triple::mips64el: - return TargetTuple::mips64el; - case Triple::msp430: - return TargetTuple::msp430; - case Triple::ppc: - return TargetTuple::ppc; - case Triple::ppc64: - return TargetTuple::ppc64; - case Triple::ppc64le: - return TargetTuple::ppc64le; - case Triple::r600: - return TargetTuple::r600; - case Triple::amdgcn: - return TargetTuple::amdgcn; - case Triple::sparc: - return TargetTuple::sparc; - case Triple::sparcv9: - return TargetTuple::sparcv9; - case Triple::sparcel: - return TargetTuple::sparcel; - case Triple::systemz: - return TargetTuple::systemz; - case Triple::tce: - return TargetTuple::tce; - case Triple::thumb: - return TargetTuple::thumb; - case Triple::thumbeb: - return TargetTuple::thumbeb; - case Triple::x86: - return TargetTuple::x86; - case Triple::x86_64: - return TargetTuple::x86_64; - case Triple::xcore: - return TargetTuple::xcore; - case Triple::nvptx: - return TargetTuple::nvptx; - case Triple::nvptx64: - return TargetTuple::nvptx64; - case Triple::le32: - return TargetTuple::le32; - case Triple::le64: - return TargetTuple::le64; - case Triple::amdil: - return TargetTuple::amdil; - case Triple::amdil64: - return TargetTuple::amdil64; - case Triple::hsail: - return TargetTuple::hsail; - case Triple::hsail64: - return TargetTuple::hsail64; - case Triple::spir: - return TargetTuple::spir; - case Triple::spir64: - return TargetTuple::spir64; - case Triple::kalimba: - return TargetTuple::kalimba; - case Triple::shave: - return TargetTuple::shave; - case Triple::wasm32: - return TargetTuple::wasm32; - case Triple::wasm64: - return TargetTuple::wasm64; - } - llvm_unreachable("Unmapped architecture."); -} - -// FIXME: These should be removed as soon as the Triple member is replaced. -static TargetTuple::SubArchType -convertTripleSubArchToTupleSubArch(Triple::SubArchType SubArch) { - switch (SubArch) { - case Triple::NoSubArch: - return TargetTuple::NoSubArch; - case Triple::ARMSubArch_v8_1a: - return TargetTuple::ARMSubArch_v8_1a; - case Triple::ARMSubArch_v8: - return TargetTuple::ARMSubArch_v8; - case Triple::ARMSubArch_v7: - return TargetTuple::ARMSubArch_v7; - case Triple::ARMSubArch_v7em: - return TargetTuple::ARMSubArch_v7em; - case Triple::ARMSubArch_v7m: - return TargetTuple::ARMSubArch_v7m; - case Triple::ARMSubArch_v7s: - return TargetTuple::ARMSubArch_v7s; - case Triple::ARMSubArch_v6: - return TargetTuple::ARMSubArch_v6; - case Triple::ARMSubArch_v6m: - return TargetTuple::ARMSubArch_v6m; - case Triple::ARMSubArch_v6k: - return TargetTuple::ARMSubArch_v6k; - case Triple::ARMSubArch_v6t2: - return TargetTuple::ARMSubArch_v6t2; - case Triple::ARMSubArch_v5: - return TargetTuple::ARMSubArch_v5; - case Triple::ARMSubArch_v5te: - return TargetTuple::ARMSubArch_v5te; - case Triple::ARMSubArch_v4t: - return TargetTuple::ARMSubArch_v4t; - case Triple::KalimbaSubArch_v3: - return TargetTuple::KalimbaSubArch_v3; - case Triple::KalimbaSubArch_v4: - return TargetTuple::KalimbaSubArch_v4; - case Triple::KalimbaSubArch_v5: - return TargetTuple::KalimbaSubArch_v5; - } - llvm_unreachable("Unmapped subarchitecture."); -} - -// FIXME: These should be removed as soon as the Triple member is replaced. -static TargetTuple::VendorType -convertTripleVendorToTupleVendor(Triple::VendorType Vendor) { - switch (Vendor) { - case Triple::UnknownVendor: - return TargetTuple::UnknownVendor; - case Triple::Apple: - return TargetTuple::Apple; - case Triple::PC: - return TargetTuple::PC; - case Triple::SCEI: - return TargetTuple::SCEI; - case Triple::BGP: - return TargetTuple::BGP; - case Triple::BGQ: - return TargetTuple::BGQ; - case Triple::Freescale: - return TargetTuple::Freescale; - case Triple::IBM: - return TargetTuple::IBM; - case Triple::ImaginationTechnologies: - return TargetTuple::ImaginationTechnologies; - case Triple::MipsTechnologies: - return TargetTuple::MipsTechnologies; - case Triple::NVIDIA: - return TargetTuple::NVIDIA; - case Triple::CSR: - return TargetTuple::CSR; - case Triple::Myriad: - return TargetTuple::Myriad; - } - llvm_unreachable("Unmapped vendor."); -} - -// FIXME: These should be removed as soon as the Triple member is replaced. -static TargetTuple::OSType convertTripleOSToTupleOS(Triple::OSType OS) { - switch (OS) { - case Triple::UnknownOS: - return TargetTuple::UnknownOS; - case Triple::CloudABI: - return TargetTuple::CloudABI; - case Triple::Darwin: - return TargetTuple::Darwin; - case Triple::DragonFly: - return TargetTuple::DragonFly; - case Triple::FreeBSD: - return TargetTuple::FreeBSD; - case Triple::IOS: - return TargetTuple::IOS; - case Triple::KFreeBSD: - return TargetTuple::KFreeBSD; - case Triple::Linux: - return TargetTuple::Linux; - case Triple::Lv2: - return TargetTuple::Lv2; - case Triple::MacOSX: - return TargetTuple::MacOSX; - case Triple::NetBSD: - return TargetTuple::NetBSD; - case Triple::OpenBSD: - return TargetTuple::OpenBSD; - case Triple::Solaris: - return TargetTuple::Solaris; - case Triple::Win32: - return TargetTuple::Win32; - case Triple::Haiku: - return TargetTuple::Haiku; - case Triple::Minix: - return TargetTuple::Minix; - case Triple::RTEMS: - return TargetTuple::RTEMS; - case Triple::NaCl: - return TargetTuple::NaCl; - case Triple::CNK: - return TargetTuple::CNK; - case Triple::Bitrig: - return TargetTuple::Bitrig; - case Triple::AIX: - return TargetTuple::AIX; - case Triple::CUDA: - return TargetTuple::CUDA; - case Triple::NVCL: - return TargetTuple::NVCL; - case Triple::AMDHSA: - return TargetTuple::AMDHSA; - case Triple::PS4: - return TargetTuple::PS4; - } - llvm_unreachable("Unmapped OS."); -} - -// FIXME: These should be removed as soon as the Triple member is replaced. -static TargetTuple::EnvironmentType -convertTripleEnvToTupleEnv(Triple::EnvironmentType Env) { - switch (Env) { - case Triple::UnknownEnvironment: - return TargetTuple::UnknownEnvironment; - case Triple::GNU: - return TargetTuple::GNU; - case Triple::GNUEABI: - return TargetTuple::GNUEABI; - case Triple::GNUEABIHF: - return TargetTuple::GNUEABIHF; - case Triple::GNUX32: - return TargetTuple::GNUX32; - case Triple::CODE16: - return TargetTuple::CODE16; - case Triple::EABI: - return TargetTuple::EABI; - case Triple::EABIHF: - return TargetTuple::EABIHF; - case Triple::Android: - return TargetTuple::Android; - case Triple::MSVC: - return TargetTuple::MSVC; - case Triple::Itanium: - return TargetTuple::Itanium; - case Triple::Cygnus: - return TargetTuple::Cygnus; - case Triple::AMDOpenCL: - return TargetTuple::AMDOpenCL; - case Triple::CoreCLR: - return TargetTuple::CoreCLR; - } - llvm_unreachable("Unmapped Environment."); -} - -// FIXME: These should be removed as soon as the Triple member is replaced. -static TargetTuple::ObjectFormatType -convertTripleObjFmtToTupleObjFmt(Triple::ObjectFormatType ObjFmt) { - switch (ObjFmt) { - case Triple::UnknownObjectFormat: - return TargetTuple::UnknownObjectFormat; - case Triple::COFF: - return TargetTuple::COFF; - case Triple::ELF: - return TargetTuple::ELF; - case Triple::MachO: - return TargetTuple::MachO; - } - llvm_unreachable("Unmapped Object Format."); -} - -TargetTuple::ArchType TargetTuple::getArch() const { - return convertTripleArchToTupleArch(GnuTT.getArch()); -} - -TargetTuple::SubArchType TargetTuple::getSubArch() const { - return convertTripleSubArchToTupleSubArch(GnuTT.getSubArch()); -} - -TargetTuple::VendorType TargetTuple::getVendor() const { - return convertTripleVendorToTupleVendor(GnuTT.getVendor()); -} - -TargetTuple::OSType TargetTuple::getOS() const { - return convertTripleOSToTupleOS(GnuTT.getOS()); -} - -TargetTuple::EnvironmentType TargetTuple::getEnvironment() const { - return convertTripleEnvToTupleEnv(GnuTT.getEnvironment()); -} - -TargetTuple::ObjectFormatType TargetTuple::getObjectFormat() const { - return convertTripleObjFmtToTupleObjFmt(GnuTT.getObjectFormat()); -} diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index aedac658745..6dfa0af4f88 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -45,7 +45,7 @@ AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) { AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian) - : AArch64GenSubtargetInfo(TargetTuple(TT), CPU, FS), ARMProcFamily(Others), + : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), HasV8_1aOps(false), HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false), HasPerfMon(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false), StrictAlign(false), ReserveX18(false), diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 56380653de5..62320218207 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -19,7 +19,6 @@ #include "AArch64InstrInfo.h" #include "AArch64RegisterInfo.h" #include "AArch64SelectionDAGInfo.h" -#include "llvm/ADT/TargetTuple.h" #include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetSubtargetInfo.h" #include <string> @@ -98,8 +97,6 @@ public: return &getInstrInfo()->getRegisterInfo(); } const Triple &getTargetTriple() const { return TargetTriple; } - // FIXME: Return a references once our member is a TargetTuple. - const TargetTuple getTargetTuple() const { return TargetTuple(TargetTriple); } bool enableMachineScheduler() const override { return true; } bool enablePostRAScheduler() const override { return isCortexA53() || isCortexA57(); diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 996ad70671b..db9fb0e775d 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -227,10 +227,11 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); } -static MCSymbolizer *createAArch64ExternalSymbolizer( - const TargetTuple &TT, LLVMOpInfoCallback GetOpInfo, - LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, - std::unique_ptr<MCRelocationInfo> &&RelInfo) { +static MCSymbolizer * +createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, + LLVMSymbolLookupCallback SymbolLookUp, + void *DisInfo, MCContext *Ctx, + std::unique_ptr<MCRelocationInfo> &&RelInfo) { return new llvm::AArch64ExternalSymbolizer(*Ctx, move(RelInfo), GetOpInfo, SymbolLookUp, DisInfo); } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp index 99d85c5de6a..7624c7240d6 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp @@ -10,7 +10,7 @@ #include "AArch64.h" #include "AArch64RegisterInfo.h" #include "MCTargetDesc/AArch64FixupKinds.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCDirectives.h" #include "llvm/MC/MCELFObjectWriter.h" @@ -521,23 +521,23 @@ void ELFAArch64AsmBackend::applyFixup(const MCFixup &Fixup, char *Data, MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, + const Triple &TheTriple, StringRef CPU) { - if (TT.isOSBinFormatMachO()) + if (TheTriple.isOSBinFormatMachO()) return new DarwinAArch64AsmBackend(T, MRI); - assert(TT.isOSBinFormatELF() && "Expect either MachO or ELF target"); - uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); + assert(TheTriple.isOSBinFormatELF() && "Expect either MachO or ELF target"); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/true); } MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, + const Triple &TheTriple, StringRef CPU) { - assert(TT.isOSBinFormatELF() && + assert(TheTriple.isOSBinFormatELF() && "Big endian is only supported for ELF targets!"); - uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/false); } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp index ac6e90106de..16d53569b23 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp @@ -17,7 +17,6 @@ #include "llvm/MC/MCELFStreamer.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/ADT/TargetTuple.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAsmInfo.h" @@ -199,7 +198,7 @@ MCELFStreamer *createAArch64ELFStreamer(MCContext &Context, MCAsmBackend &TAB, MCTargetStreamer * createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { - const TargetTuple &TT = STI.getTargetTuple(); + const Triple &TT = STI.getTargetTriple(); if (TT.isOSBinFormatELF()) return new AArch64TargetELFStreamer(S); return nullptr; diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp index 8f84f54d6ae..921c4b94a72 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #include "AArch64MCAsmInfo.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCStreamer.h" @@ -69,8 +69,8 @@ const MCExpr *AArch64MCAsmInfoDarwin::getExprForPersonalitySymbol( return MCBinaryExpr::createSub(Res, PC, Context); } -AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const TargetTuple &T) { - if (T.getArch() == TargetTuple::aarch64_be) +AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const Triple &T) { + if (T.getArch() == Triple::aarch64_be) IsLittleEndian = false; // We prefer NEON instructions to be printed in the short form. diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h index 586a7975535..253cd30f26e 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h @@ -20,7 +20,7 @@ namespace llvm { class MCStreamer; class Target; -class TargetTuple; +class Triple; struct AArch64MCAsmInfoDarwin : public MCAsmInfoDarwin { explicit AArch64MCAsmInfoDarwin(); @@ -30,7 +30,7 @@ struct AArch64MCAsmInfoDarwin : public MCAsmInfoDarwin { }; struct AArch64MCAsmInfoELF : public MCAsmInfoELF { - explicit AArch64MCAsmInfoELF(const TargetTuple &TT); + explicit AArch64MCAsmInfoELF(const Triple &T); }; } // namespace llvm diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp index 953ba9ec17c..9f7bed0d3b1 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -40,29 +40,28 @@ static MCInstrInfo *createAArch64MCInstrInfo() { return X; } -static MCSubtargetInfo *createAArch64MCSubtargetInfo(const TargetTuple &TT, - StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { if (CPU.empty()) CPU = "generic"; return createAArch64MCSubtargetInfoImpl(TT, CPU, FS); } -static MCRegisterInfo *createAArch64MCRegisterInfo(const TargetTuple &TT) { +static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) { MCRegisterInfo *X = new MCRegisterInfo(); InitAArch64MCRegisterInfo(X, AArch64::LR); return X; } static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, - const TargetTuple &TT) { + const Triple &TheTriple) { MCAsmInfo *MAI; - if (TT.isOSBinFormatMachO()) + if (TheTriple.isOSBinFormatMachO()) MAI = new AArch64MCAsmInfoDarwin(); else { - assert(TT.isOSBinFormatELF() && "Only expect Darwin or ELF"); - MAI = new AArch64MCAsmInfoELF(TT); + assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF"); + MAI = new AArch64MCAsmInfoELF(TheTriple); } // Initial state of the frame pointer is SP. @@ -73,7 +72,7 @@ static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createAArch64MCCodeGenInfo(const TargetTuple &TT, +static MCCodeGenInfo *createAArch64MCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -105,7 +104,7 @@ static MCCodeGenInfo *createAArch64MCCodeGenInfo(const TargetTuple &TT, return X; } -static MCInstPrinter *createAArch64MCInstPrinter(const TargetTuple &TT, +static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, @@ -118,7 +117,7 @@ static MCInstPrinter *createAArch64MCInstPrinter(const TargetTuple &TT, return nullptr; } -static MCStreamer *createELFStreamer(const TargetTuple &TT, MCContext &Ctx, +static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, MCAsmBackend &TAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll) { return createAArch64ELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll); diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h index 98a12874278..342384437c6 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h @@ -31,7 +31,7 @@ class MCSubtargetInfo; class MCTargetStreamer; class StringRef; class Target; -class TargetTuple; +class Triple; class raw_ostream; class raw_pwrite_stream; @@ -44,10 +44,10 @@ MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); MCAsmBackend *createAArch64leAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCAsmBackend *createAArch64beAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index c6cb8f9544a..5f32a65c933 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -63,13 +63,13 @@ AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT, AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS, TargetMachine &TM) - : AMDGPUGenSubtargetInfo(TargetTuple(TT), GPU, FS), DevName(GPU), - Is64bit(false), DumpCode(false), R600ALUInst(false), - HasVertexCache(false), TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), - FP64(false), FP64Denormals(false), FP32Denormals(false), - FastFMAF32(false), CaymanISA(false), FlatAddressSpace(false), - EnableIRStructurizer(true), EnablePromoteAlloca(false), EnableIfCvt(true), - EnableLoadStoreOpt(false), EnableUnsafeDSOffsetFolding(false), + : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false), + DumpCode(false), R600ALUInst(false), HasVertexCache(false), + TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false), + FP64Denormals(false), FP32Denormals(false), FastFMAF32(false), + CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true), + EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false), + EnableUnsafeDSOffsetFolding(false), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0), EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false), GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0), diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp index 5d93b73c0df..4434d9b119c 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -174,8 +174,9 @@ public: MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { + Triple TargetTriple(TT); + // Use 64-bit ELF for amdgcn - return new ELFAMDGPUAsmBackend(T, TT.getArch() == TargetTuple::amdgcn); + return new ELFAMDGPUAsmBackend(T, TargetTriple.getArch() == Triple::amdgcn); } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp index 50fb64c0a97..028a86dfc7a 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp @@ -11,7 +11,7 @@ #include "AMDGPUMCAsmInfo.h" using namespace llvm; -AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const TargetTuple &TT) : MCAsmInfoELF() { +AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT) : MCAsmInfoELF() { HasSingleParameterDotFile = false; //===------------------------------------------------------------------===// MaxInstLength = 16; diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h index de6334c5d45..119dd425916 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h @@ -17,7 +17,7 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class TargetTuple; +class Triple; // If you need to create another MCAsmInfo class, which inherits from MCAsmInfo, // you will need to make sure your new class sets PrivateGlobalPrefix to @@ -26,7 +26,7 @@ class TargetTuple; // with 'L' as a local symbol. class AMDGPUMCAsmInfo : public MCAsmInfoELF { public: - explicit AMDGPUMCAsmInfo(const TargetTuple &TT); + explicit AMDGPUMCAsmInfo(const Triple &TT); }; } // namespace llvm #endif diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp index b690926eeef..c709741f377 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -44,19 +44,18 @@ static MCInstrInfo *createAMDGPUMCInstrInfo() { return X; } -static MCRegisterInfo *createAMDGPUMCRegisterInfo(const TargetTuple &TT) { +static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); InitAMDGPUMCRegisterInfo(X, 0); return X; } -static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(const TargetTuple &TT, - StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS); } -static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const TargetTuple &TT, +static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -65,7 +64,7 @@ static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(const TargetTuple &TT, return X; } -static MCInstPrinter *createAMDGPUMCInstPrinter(const TargetTuple &T, +static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h index 958e967c05d..5d1b86b8c0c 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -28,7 +28,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; class Target; -class TargetTuple; +class Triple; class raw_pwrite_stream; class raw_ostream; @@ -44,7 +44,7 @@ MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit, raw_pwrite_stream &OS); diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index 3a8556e4af7..f5f12472437 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -558,7 +558,7 @@ void ARMAsmPrinter::emitAttributes() { const Triple &TT = TM.getTargetTriple(); StringRef CPU = TM.getTargetCPU(); StringRef FS = TM.getTargetFeatureString(); - std::string ArchFS = ARM_MC::ParseARMTargetTuple(TargetTuple(TT), CPU); + std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); if (!FS.empty()) { if (!ArchFS.empty()) ArchFS = (Twine(ArchFS) + "," + FS).str(); diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 0f2069474be..50e9e6a7397 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -81,7 +81,7 @@ ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU, ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle) - : ARMGenSubtargetInfo(TargetTuple(TT), CPU, FS), ARMProcFamily(Others), + : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)), @@ -159,8 +159,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { // Insert the architecture feature derived from the target triple into the // feature string. This is important for setting features that are implied // based on the architecture version. - std::string ArchFS = - ARM_MC::ParseARMTargetTuple(TargetTuple(TargetTriple), CPUString); + std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString); if (!FS.empty()) { if (!ArchFS.empty()) ArchFS = (Twine(ArchFS) + "," + FS).str(); diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index ada3aa7d2a3..1fe2dbe7866 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -779,49 +779,45 @@ static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) { MCAsmBackend *llvm::createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU, + const Triple &TheTriple, StringRef CPU, bool isLittle) { - switch (TT.getObjectFormat()) { + switch (TheTriple.getObjectFormat()) { default: llvm_unreachable("unsupported object format"); - case TargetTuple::MachO: { - MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TT.getArchName()); - return new ARMAsmBackendDarwin(T, TT, CS); - } - case TargetTuple::COFF: - assert(TT.isOSWindows() && "non-Windows ARM COFF is not supported"); - return new ARMAsmBackendWinCOFF(T, TT); - case TargetTuple::ELF: - assert(TT.isOSBinFormatELF() && "using ELF for non-ELF target"); - uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); - return new ARMAsmBackendELF(T, TT, OSABI, isLittle); + case Triple::MachO: { + MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName()); + return new ARMAsmBackendDarwin(T, TheTriple, CS); + } + case Triple::COFF: + assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); + return new ARMAsmBackendWinCOFF(T, TheTriple); + case Triple::ELF: + assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target"); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); + return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle); } } MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return createARMAsmBackend(T, MRI, TT, CPU, true); } MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return createARMAsmBackend(T, MRI, TT, CPU, false); } MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return createARMAsmBackend(T, MRI, TT, CPU, true); } MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return createARMAsmBackend(T, MRI, TT, CPU, false); } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h index ff007320f41..6b4abd5898e 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h @@ -23,7 +23,7 @@ class ARMAsmBackend : public MCAsmBackend { bool isThumbMode; // Currently emitting Thumb code. bool IsLittleEndian; // Big or little endian. public: - ARMAsmBackend(const Target &T, const TargetTuple &TT, bool IsLittle) + ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle) : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), isThumbMode(TT.getArchName().startswith("thumb")), IsLittleEndian(IsLittle) {} diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h index b25f0a1bf9b..a6206e3d958 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h @@ -18,7 +18,7 @@ namespace { class ARMAsmBackendDarwin : public ARMAsmBackend { public: const MachO::CPUSubTypeARM Subtype; - ARMAsmBackendDarwin(const Target &T, const TargetTuple &TT, + ARMAsmBackendDarwin(const Target &T, const Triple &TT, MachO::CPUSubTypeARM st) : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), Subtype(st) { HasDataInCodeSupport = true; diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h index 84d319146bb..68b12edd089 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h @@ -15,7 +15,7 @@ namespace { class ARMAsmBackendELF : public ARMAsmBackend { public: uint8_t OSABI; - ARMAsmBackendELF(const Target &T, const TargetTuple &TT, uint8_t OSABI, + ARMAsmBackendELF(const Target &T, const Triple &TT, uint8_t OSABI, bool IsLittle) : ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) {} diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h index d5783b14c83..170f59a4c90 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h @@ -15,8 +15,8 @@ using namespace llvm; namespace { class ARMAsmBackendWinCOFF : public ARMAsmBackend { public: - ARMAsmBackendWinCOFF(const Target &T, const TargetTuple &TT) - : ARMAsmBackend(T, TT, true) {} + ARMAsmBackendWinCOFF(const Target &T, const Triple &TheTriple) + : ARMAsmBackend(T, TheTriple, true) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false); } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp index b858f1f82ee..a969d30041a 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -1361,7 +1361,7 @@ MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S) { MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { - const TargetTuple &TT = STI.getTargetTuple(); + const Triple &TT = STI.getTargetTriple(); if (TT.isOSBinFormatELF()) return new ARMTargetELFStreamer(S); return new ARMTargetStreamer(S); diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp index 90746468fe9..1ac08159bd3 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp @@ -12,16 +12,16 @@ //===----------------------------------------------------------------------===// #include "ARMMCAsmInfo.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" #include "llvm/Support/CommandLine.h" using namespace llvm; void ARMMCAsmInfoDarwin::anchor() { } -ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const TargetTuple &TT) { - if ((TT.getArch() == TargetTuple::armeb) || - (TT.getArch() == TargetTuple::thumbeb)) +ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const Triple &TheTriple) { + if ((TheTriple.getArch() == Triple::armeb) || + (TheTriple.getArch() == Triple::thumbeb)) IsLittleEndian = false; Data64bitsDirective = nullptr; @@ -40,9 +40,9 @@ ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const TargetTuple &TT) { void ARMELFMCAsmInfo::anchor() { } -ARMELFMCAsmInfo::ARMELFMCAsmInfo(const TargetTuple &TT) { - if ((TT.getArch() == TargetTuple::armeb) || - (TT.getArch() == TargetTuple::thumbeb)) +ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) { + if ((TheTriple.getArch() == Triple::armeb) || + (TheTriple.getArch() == Triple::thumbeb)) IsLittleEndian = false; // ".comm align is in bytes but .align is pow-2." @@ -56,9 +56,9 @@ ARMELFMCAsmInfo::ARMELFMCAsmInfo(const TargetTuple &TT) { SupportsDebugInformation = true; // Exceptions handling - switch (TT.getOS()) { - case TargetTuple::Bitrig: - case TargetTuple::NetBSD: + switch (TheTriple.getOS()) { + case Triple::Bitrig: + case Triple::NetBSD: ExceptionsType = ExceptionHandling::DwarfCFI; break; default: diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h index 8e121a5b967..5e548162bec 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h @@ -19,20 +19,20 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class TargetTuple; +class Triple; class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin { virtual void anchor(); public: - explicit ARMMCAsmInfoDarwin(const TargetTuple &TT); + explicit ARMMCAsmInfoDarwin(const Triple &TheTriple); }; class ARMELFMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit ARMELFMCAsmInfo(const TargetTuple &TT); + explicit ARMELFMCAsmInfo(const Triple &TT); void setUseIntegratedAssembler(bool Value) override; }; diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index ba2b6b1d03a..b88578309f0 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -57,7 +57,7 @@ public: return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2]; } bool isTargetMachO(const MCSubtargetInfo &STI) const { - const TargetTuple &TT = STI.getTargetTuple(); + const Triple &TT = STI.getTargetTriple(); return TT.isOSBinFormatMachO(); } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index e2a26a7b487..21c9fc1e58b 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -15,7 +15,7 @@ #include "ARMMCAsmInfo.h" #include "ARMMCTargetDesc.h" #include "InstPrinter/ARMInstPrinter.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCInstrAnalysis.h" @@ -130,16 +130,16 @@ static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, #define GET_SUBTARGETINFO_MC_DESC #include "ARMGenSubtargetInfo.inc" -std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) { - bool isThumb = TT.getArch() == TargetTuple::thumb || - TT.getArch() == TargetTuple::thumbeb; +std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) { + bool isThumb = + TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb; bool NoCPU = CPU == "generic" || CPU.empty(); std::string ARMArchFeature; switch (TT.getSubArch()) { default: llvm_unreachable("invalid sub-architecture for ARM"); - case TargetTuple::ARMSubArch_v8: + case Triple::ARMSubArch_v8: if (NoCPU) // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2, // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, @@ -150,7 +150,7 @@ std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) { // Use CPU to figure out the exact features ARMArchFeature = "+v8"; break; - case TargetTuple::ARMSubArch_v8_1a: + case Triple::ARMSubArch_v8_1a: if (NoCPU) // v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2, // FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone, @@ -161,7 +161,7 @@ std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) { // Use CPU to figure out the exact features ARMArchFeature = "+v8.1a"; break; - case TargetTuple::ARMSubArch_v7m: + case Triple::ARMSubArch_v7m: isThumb = true; if (NoCPU) // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass @@ -170,7 +170,7 @@ std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) { // Use CPU to figure out the exact features. ARMArchFeature = "+v7"; break; - case TargetTuple::ARMSubArch_v7em: + case Triple::ARMSubArch_v7em: if (NoCPU) // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2, // FeatureT2XtPk, FeatureMClass @@ -179,7 +179,7 @@ std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) { // Use CPU to figure out the exact features. ARMArchFeature = "+v7"; break; - case TargetTuple::ARMSubArch_v7s: + case Triple::ARMSubArch_v7s: if (NoCPU) // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS // Swift @@ -188,7 +188,7 @@ std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) { // Use CPU to figure out the exact features. ARMArchFeature = "+v7"; break; - case TargetTuple::ARMSubArch_v7: + case Triple::ARMSubArch_v7: // v7 CPUs have lots of different feature sets. If no CPU is specified, // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return // the "minimum" feature set and use CPU string to figure out the exact @@ -200,13 +200,13 @@ std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) { // Use CPU to figure out the exact features. ARMArchFeature = "+v7"; break; - case TargetTuple::ARMSubArch_v6t2: + case Triple::ARMSubArch_v6t2: ARMArchFeature = "+v6t2"; break; - case TargetTuple::ARMSubArch_v6k: + case Triple::ARMSubArch_v6k: ARMArchFeature = "+v6k"; break; - case TargetTuple::ARMSubArch_v6m: + case Triple::ARMSubArch_v6m: isThumb = true; if (NoCPU) // v6m: FeatureNoARM, FeatureMClass @@ -214,19 +214,19 @@ std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) { else ARMArchFeature = "+v6"; break; - case TargetTuple::ARMSubArch_v6: + case Triple::ARMSubArch_v6: ARMArchFeature = "+v6"; break; - case TargetTuple::ARMSubArch_v5te: + case Triple::ARMSubArch_v5te: ARMArchFeature = "+v5te"; break; - case TargetTuple::ARMSubArch_v5: + case Triple::ARMSubArch_v5: ARMArchFeature = "+v5t"; break; - case TargetTuple::ARMSubArch_v4t: + case Triple::ARMSubArch_v4t: ARMArchFeature = "+v4t"; break; - case TargetTuple::NoSubArch: + case Triple::NoSubArch: break; } @@ -247,9 +247,9 @@ std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) { return ARMArchFeature; } -MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const TargetTuple &TT, +MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { - std::string ArchFS = ARM_MC::ParseARMTargetTuple(TT, CPU); + std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU); if (!FS.empty()) { if (!ArchFS.empty()) ArchFS = (Twine(ArchFS) + "," + FS).str(); @@ -266,23 +266,23 @@ static MCInstrInfo *createARMMCInstrInfo() { return X; } -static MCRegisterInfo *createARMMCRegisterInfo(const TargetTuple &TT) { +static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) { MCRegisterInfo *X = new MCRegisterInfo(); InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC); return X; } static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, - const TargetTuple &TT) { + const Triple &TheTriple) { MCAsmInfo *MAI; - if (TT.isOSDarwin() || TT.isOSBinFormatMachO()) - MAI = new ARMMCAsmInfoDarwin(TT); - else if (TT.isWindowsMSVCEnvironment()) + if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO()) + MAI = new ARMMCAsmInfoDarwin(TheTriple); + else if (TheTriple.isWindowsMSVCEnvironment()) MAI = new ARMCOFFMCAsmInfoMicrosoft(); - else if (TT.isOSWindows()) + else if (TheTriple.isOSWindows()) MAI = new ARMCOFFMCAsmInfoGNU(); else - MAI = new ARMELFMCAsmInfo(TT); + MAI = new ARMELFMCAsmInfo(TheTriple); unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0)); @@ -290,8 +290,7 @@ static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createARMMCCodeGenInfo(const TargetTuple &TT, - Reloc::Model RM, +static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { MCCodeGenInfo *X = new MCCodeGenInfo(); @@ -303,11 +302,11 @@ static MCCodeGenInfo *createARMMCCodeGenInfo(const TargetTuple &TT, return X; } -static MCStreamer *createELFStreamer(const TargetTuple &TT, MCContext &Ctx, +static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll) { return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, - TT.getArch() == TargetTuple::thumb); + T.getArch() == Triple::thumb); } static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB, @@ -317,7 +316,7 @@ static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB, return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd); } -static MCInstPrinter *createARMMCInstPrinter(const TargetTuple &TT, +static MCInstPrinter *createARMMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, @@ -327,7 +326,7 @@ static MCInstPrinter *createARMMCInstPrinter(const TargetTuple &TT, return nullptr; } -static MCRelocationInfo *createARMMCRelocationInfo(const TargetTuple &TT, +static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT, MCContext &Ctx) { if (TT.isOSBinFormatMachO()) return createARMMachORelocationInfo(Ctx); diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h index 0619f308909..fd30623d79a 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h @@ -32,7 +32,7 @@ class MCRelocationInfo; class MCTargetStreamer; class StringRef; class Target; -class TargetTuple; +class Triple; class raw_ostream; class raw_pwrite_stream; @@ -40,11 +40,11 @@ extern Target TheARMLETarget, TheThumbLETarget; extern Target TheARMBETarget, TheThumbBETarget; namespace ARM_MC { -std::string ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU); +std::string ParseARMTriple(const Triple &TT, StringRef CPU); /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc. /// do not need to go through TargetRegistry. -MCSubtargetInfo *createARMMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, +MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS); } @@ -65,22 +65,22 @@ MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU, + const Triple &TT, StringRef CPU, bool IsLittleEndian); MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); // Construct a PE/COFF machine code streamer which will generate a PE/COFF // object file. diff --git a/llvm/lib/Target/BPF/BPFSubtarget.cpp b/llvm/lib/Target/BPF/BPFSubtarget.cpp index 4debc99ce35..c3a8b1caa63 100644 --- a/llvm/lib/Target/BPF/BPFSubtarget.cpp +++ b/llvm/lib/Target/BPF/BPFSubtarget.cpp @@ -27,5 +27,5 @@ void BPFSubtarget::anchor() {} BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) - : BPFGenSubtargetInfo(TargetTuple(TT), CPU, FS), InstrInfo(), - FrameLowering(*this), TLInfo(TM, *this) {} + : BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this), + TLInfo(TM, *this) {} diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp b/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp index b611c3d827d..8c358cab62e 100644 --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp @@ -95,13 +95,12 @@ MCObjectWriter *BPFAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const { MCAsmBackend *llvm::createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU) { + const Triple &TT, StringRef CPU) { return new BPFAsmBackend(/*IsLittleEndian=*/true); } MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return new BPFAsmBackend(/*IsLittleEndian=*/false); } diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h index c22790e86aa..1f440fe8787 100644 --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h @@ -16,15 +16,16 @@ #include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmInfo.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" namespace llvm { class Target; +class Triple; class BPFMCAsmInfo : public MCAsmInfo { public: - explicit BPFMCAsmInfo(const TargetTuple &TT) { - if (TT.getArch() == TargetTuple::bpfeb) + explicit BPFMCAsmInfo(const Triple &TT) { + if (TT.getArch() == Triple::bpfeb) IsLittleEndian = false; PrivateGlobalPrefix = ".L"; diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp index 5dfb006f797..840570ebc39 100644 --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp @@ -40,19 +40,18 @@ static MCInstrInfo *createBPFMCInstrInfo() { return X; } -static MCRegisterInfo *createBPFMCRegisterInfo(const TargetTuple &TT) { +static MCRegisterInfo *createBPFMCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); InitBPFMCRegisterInfo(X, BPF::R11 /* RAReg doesn't exist */); return X; } -static MCSubtargetInfo *createBPFMCSubtargetInfo(const TargetTuple &TT, +static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createBPFMCSubtargetInfoImpl(TT, CPU, FS); } -static MCCodeGenInfo *createBPFMCCodeGenInfo(const TargetTuple &TT, - Reloc::Model RM, +static MCCodeGenInfo *createBPFMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { MCCodeGenInfo *X = new MCCodeGenInfo(); @@ -60,13 +59,14 @@ static MCCodeGenInfo *createBPFMCCodeGenInfo(const TargetTuple &TT, return X; } -static MCStreamer *createBPFMCStreamer(const TargetTuple &TT, MCContext &Ctx, - MCAsmBackend &MAB, raw_pwrite_stream &OS, - MCCodeEmitter *Emitter, bool RelaxAll) { +static MCStreamer *createBPFMCStreamer(const Triple &T, + MCContext &Ctx, MCAsmBackend &MAB, + raw_pwrite_stream &OS, MCCodeEmitter *Emitter, + bool RelaxAll) { return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll); } -static MCInstPrinter *createBPFMCInstPrinter(const TargetTuple &TT, +static MCInstPrinter *createBPFMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, diff --git a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h index 83f3ec2e238..e2ae6526edc 100644 --- a/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h +++ b/llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h @@ -27,7 +27,7 @@ class MCRegisterInfo; class MCSubtargetInfo; class StringRef; class Target; -class TargetTuple; +class Triple; class raw_ostream; class raw_pwrite_stream; @@ -43,9 +43,9 @@ MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian); diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 31c43b0cd74..cd482b3e3af 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -72,7 +72,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) - : HexagonGenSubtargetInfo(TargetTuple(TT), CPU, FS), CPUString(CPU), + : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), FrameLowering() { diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index 105e78f3cb9..99ea2fabf86 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -309,7 +309,7 @@ public: namespace llvm { MCAsmBackend *createHexagonAsmBackend(Target const &T, MCRegisterInfo const & /*MRI*/, - const TargetTuple &TT, StringRef CPU) { + const Triple &TT, StringRef CPU) { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); return new HexagonAsmBackend(T, OSABI, CPU); } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp index 113b622a4f0..51d2f1c878d 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -18,7 +18,7 @@ using namespace llvm; // Pin the vtable to this file. void HexagonMCAsmInfo::anchor() {} -HexagonMCAsmInfo::HexagonMCAsmInfo(const TargetTuple &TT) { +HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) { Data16bitsDirective = "\t.half\t"; Data32bitsDirective = "\t.word\t"; Data64bitsDirective = nullptr; // .xword is only supported by V9. diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h index de9702ea789..a8456b4ead9 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h @@ -18,13 +18,13 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class TargetTuple; +class Triple; class HexagonMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit HexagonMCAsmInfo(const TargetTuple &TT); + explicit HexagonMCAsmInfo(const Triple &TT); }; } // namespace llvm diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index ca426345187..53305d85fd8 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -46,15 +46,14 @@ MCInstrInfo *llvm::createHexagonMCInstrInfo() { return X; } -static MCRegisterInfo *createHexagonMCRegisterInfo(const TargetTuple &TT) { +static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); InitHexagonMCRegisterInfo(X, Hexagon::R0); return X; } -static MCSubtargetInfo *createHexagonMCSubtargetInfo(const TargetTuple &TT, - StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createHexagonMCSubtargetInfoImpl(TT, CPU, FS); } @@ -139,7 +138,7 @@ public: } static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, - const TargetTuple &TT) { + const Triple &TT) { MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); // VirtualFP = (R30 + #0). @@ -150,7 +149,7 @@ static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createHexagonMCCodeGenInfo(const TargetTuple &TT, +static MCCodeGenInfo *createHexagonMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -161,7 +160,7 @@ static MCCodeGenInfo *createHexagonMCCodeGenInfo(const TargetTuple &TT, return X; } -static MCInstPrinter *createHexagonMCInstPrinter(const TargetTuple &TT, +static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, @@ -179,7 +178,7 @@ static MCTargetStreamer *createMCAsmTargetStreamer(MCStreamer &S, return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *InstPrint); } -static MCStreamer *createMCStreamer(const TargetTuple &TT, MCContext &Context, +static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll) { return createHexagonELFStreamer(Context, MAB, OS, Emitter); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h index a5c23bdfdaa..cb626503313 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -27,7 +27,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; class Target; -class TargetTuple; +class Triple; class StringRef; class raw_ostream; class raw_pwrite_stream; @@ -44,7 +44,7 @@ MCCodeEmitter *createHexagonMCCodeEmitter(MCInstrInfo const &MCII, MCAsmBackend *createHexagonAsmBackend(Target const &T, MCRegisterInfo const &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU); diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp index 3c744aa64ab..c26b3081dbc 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp @@ -16,7 +16,7 @@ using namespace llvm; void MSP430MCAsmInfo::anchor() { } -MSP430MCAsmInfo::MSP430MCAsmInfo(const TargetTuple &TT) { +MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT) { PointerSize = CalleeSaveStackSlotSize = 2; CommentString = ";"; diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h index 93a00724de1..183dee36a04 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h @@ -17,13 +17,13 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class TargetTuple; +class Triple; class MSP430MCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit MSP430MCAsmInfo(const TargetTuple &TT); + explicit MSP430MCAsmInfo(const Triple &TT); }; } // namespace llvm diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp index 66e834126d5..807d1129b5f 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -37,19 +37,18 @@ static MCInstrInfo *createMSP430MCInstrInfo() { return X; } -static MCRegisterInfo *createMSP430MCRegisterInfo(const TargetTuple &TT) { +static MCRegisterInfo *createMSP430MCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); InitMSP430MCRegisterInfo(X, MSP430::PC); return X; } -static MCSubtargetInfo *createMSP430MCSubtargetInfo(const TargetTuple &TT, - StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createMSP430MCSubtargetInfoImpl(TT, CPU, FS); } -static MCCodeGenInfo *createMSP430MCCodeGenInfo(const TargetTuple &TT, +static MCCodeGenInfo *createMSP430MCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -58,7 +57,7 @@ static MCCodeGenInfo *createMSP430MCCodeGenInfo(const TargetTuple &TT, return X; } -static MCInstPrinter *createMSP430MCInstPrinter(const TargetTuple &T, +static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, diff --git a/llvm/lib/Target/MSP430/MSP430Subtarget.cpp b/llvm/lib/Target/MSP430/MSP430Subtarget.cpp index c998e1130d9..6216348e4d7 100644 --- a/llvm/lib/Target/MSP430/MSP430Subtarget.cpp +++ b/llvm/lib/Target/MSP430/MSP430Subtarget.cpp @@ -33,5 +33,5 @@ MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) - : MSP430GenSubtargetInfo(TargetTuple(TT), CPU, FS), FrameLowering(), + : MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {} diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 5a3cf65a3c8..0bddc4ca690 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -375,8 +375,8 @@ public: MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser, const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options), STI(sti), - ABI(MipsABIInfo::computeTargetABI(sti.getTargetTuple(), sti.getCPU(), - Options)) { + ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()), + sti.getCPU(), Options)) { MCAsmParserExtension::Initialize(parser); parser.addAliasForDirective(".asciiz", ".asciz"); @@ -402,9 +402,9 @@ public: IsPicEnabled = (getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_); - const TargetTuple &TT = sti.getTargetTuple(); - if ((TT.getArch() == TargetTuple::mips) || - (TT.getArch() == TargetTuple::mips64)) + Triple TheTriple(sti.getTargetTriple()); + if ((TheTriple.getArch() == Triple::mips) || + (TheTriple.getArch() == Triple::mips64)) IsLittleEndian = false; else IsLittleEndian = true; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp index 03b5ca28c4a..bd1feb81d86 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp @@ -47,7 +47,7 @@ unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const { llvm_unreachable("Unhandled ABI"); } -MipsABIInfo MipsABIInfo::computeTargetABI(const TargetTuple &TT, StringRef CPU, +MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU, const MCTargetOptions &Options) { if (Options.getABIName().startswith("o32")) return MipsABIInfo::O32(); @@ -64,8 +64,7 @@ MipsABIInfo MipsABIInfo::computeTargetABI(const TargetTuple &TT, StringRef CPU, // used and not shared in a couple of other places. This needs unifying // at some level. if (CPU.empty() || CPU == "generic") { - if (TT.getArch() == TargetTuple::mips || - TT.getArch() == TargetTuple::mipsel) + if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel) CPU = "mips32"; else CPU = "mips64"; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h index d58e6abddd3..cb3df44c800 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h @@ -11,7 +11,7 @@ #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H #include "llvm/ADT/ArrayRef.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" #include "llvm/IR/CallingConv.h" #include "llvm/MC/MCRegisterInfo.h" @@ -36,7 +36,7 @@ public: static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); } static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); } static MipsABIInfo EABI() { return MipsABIInfo(ABI::EABI); } - static MipsABIInfo computeTargetABI(const TargetTuple &TT, StringRef CPU, + static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU, const MCTargetOptions &Options); bool IsKnown() const { return ThisABI != ABI::Unknown; } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index 13f90d434a3..328e71720ca 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -411,31 +411,27 @@ void MipsAsmBackend::processFixupValue(const MCAssembler &Asm, // MCAsmBackend MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ false); } MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, /*Is64Bit*/ false); } MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true); } MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, /*Is64Bit*/ true); } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h index 603a58fb5de..b3d5a4964f8 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -16,7 +16,7 @@ #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H #include "MCTargetDesc/MipsFixupKinds.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" #include "llvm/MC/MCAsmBackend.h" namespace llvm { @@ -27,12 +27,12 @@ class Target; class MCObjectWriter; class MipsAsmBackend : public MCAsmBackend { - TargetTuple::OSType OSType; + Triple::OSType OSType; bool IsLittle; // Big or little endian bool Is64Bit; // 32 or 64 bit words public: - MipsAsmBackend(const Target &T, TargetTuple::OSType OSType, bool IsLittle, + MipsAsmBackend(const Target &T, Triple::OSType OSType, bool IsLittle, bool Is64Bit) : MCAsmBackend(), OSType(OSType), IsLittle(IsLittle), Is64Bit(Is64Bit) {} diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp index c370c816ac7..4d554583dc7 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp @@ -12,19 +12,19 @@ //===----------------------------------------------------------------------===// #include "MipsMCAsmInfo.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" using namespace llvm; void MipsMCAsmInfo::anchor() { } -MipsMCAsmInfo::MipsMCAsmInfo(const TargetTuple &TT) { - if ((TT.getArch() == TargetTuple::mips) || - (TT.getArch() == TargetTuple::mips64)) +MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) { + if ((TheTriple.getArch() == Triple::mips) || + (TheTriple.getArch() == Triple::mips64)) IsLittleEndian = false; - if ((TT.getArch() == TargetTuple::mips64el) || - (TT.getArch() == TargetTuple::mips64)) { + if ((TheTriple.getArch() == Triple::mips64el) || + (TheTriple.getArch() == Triple::mips64)) { PointerSize = CalleeSaveStackSlotSize = 8; } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h index f7ad1f6dc5e..d4ccf0349c1 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h @@ -17,13 +17,13 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class TargetTuple; +class Triple; class MipsMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit MipsMCAsmInfo(const TargetTuple &TT); + explicit MipsMCAsmInfo(const Triple &TheTriple); }; } // namespace llvm diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index 5ef473099d1..949ee1474f9 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -17,7 +17,7 @@ #include "MipsMCNaCl.h" #include "MipsMCTargetDesc.h" #include "MipsTargetStreamer.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCInstrInfo.h" @@ -43,10 +43,9 @@ using namespace llvm; /// Select the Mips CPU for the given triple and cpu name. /// FIXME: Merge with the copy in MipsSubtarget.cpp -StringRef MIPS_MC::selectMipsCPU(const TargetTuple &TT, StringRef CPU) { +StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) { if (CPU.empty() || CPU == "generic") { - if (TT.getArch() == TargetTuple::mips || - TT.getArch() == TargetTuple::mipsel) + if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel) CPU = "mips32"; else CPU = "mips64"; @@ -60,20 +59,20 @@ static MCInstrInfo *createMipsMCInstrInfo() { return X; } -static MCRegisterInfo *createMipsMCRegisterInfo(const TargetTuple &TT) { +static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); InitMipsMCRegisterInfo(X, Mips::RA); return X; } -static MCSubtargetInfo *createMipsMCSubtargetInfo(const TargetTuple &TT, +static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { CPU = MIPS_MC::selectMipsCPU(TT, CPU); return createMipsMCSubtargetInfoImpl(TT, CPU, FS); } static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, - const TargetTuple &TT) { + const Triple &TT) { MCAsmInfo *MAI = new MipsMCAsmInfo(TT); unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); @@ -83,8 +82,7 @@ static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createMipsMCCodeGenInfo(const TargetTuple &TT, - Reloc::Model RM, +static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { MCCodeGenInfo *X = new MCCodeGenInfo(); @@ -96,7 +94,7 @@ static MCCodeGenInfo *createMipsMCCodeGenInfo(const TargetTuple &TT, return X; } -static MCInstPrinter *createMipsMCInstPrinter(const TargetTuple &T, +static MCInstPrinter *createMipsMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, @@ -104,7 +102,7 @@ static MCInstPrinter *createMipsMCInstPrinter(const TargetTuple &T, return new MipsInstPrinter(MAI, MII, MRI); } -static MCStreamer *createMCStreamer(const TargetTuple &T, MCContext &Context, +static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll) { MCStreamer *S; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h index 13f6e4045b0..4069d7d184e 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -26,7 +26,7 @@ class MCRegisterInfo; class MCSubtargetInfo; class StringRef; class Target; -class TargetTuple; +class Triple; class raw_ostream; class raw_pwrite_stream; @@ -44,22 +44,22 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, MCAsmBackend *createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCAsmBackend *createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCAsmBackend *createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCAsmBackend *createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian, bool Is64Bit); namespace MIPS_MC { -StringRef selectMipsCPU(const TargetTuple &TT, StringRef CPU); +StringRef selectMipsCPU(const Triple &TT, StringRef CPU); } } // End llvm namespace diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 55d97e26a96..c2e176c2c6a 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -693,12 +693,11 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { // clean anyhow. // FIXME: For ifunc related functions we could iterate over and look // for a feature string that doesn't match the default one. - TargetTuple TT(TargetTuple(TM.getTargetTriple())); + const Triple &TT = TM.getTargetTriple(); StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU()); StringRef FS = TM.getTargetFeatureString(); const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM); - const MipsSubtarget STI(TM.getTargetTriple(), CPU, FS, MTM.isLittleEndian(), - MTM); + const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM); bool IsABICalls = STI.isABICalls(); const MipsABIInfo &ABI = MTM.getABI(); diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp index 4d2dc07644f..bb23a399f48 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -62,16 +62,16 @@ void MipsSubtarget::anchor() { } MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, bool little, const MipsTargetMachine &TM) - : MipsGenSubtargetInfo(TargetTuple(TT), CPU, FS), - MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false), - IsSingleFloat(false), IsFPXX(false), NoABICalls(false), IsFP64bit(false), - UseOddSPReg(true), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), - HasCnMips(false), HasMips3_32(false), HasMips3_32r2(false), - HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false), - InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), - InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), - AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), - UseTCCInDIV(false), HasEVA(false), TM(TM), TargetTriple(TT), TSInfo(), + : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault), + IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false), + NoABICalls(false), IsFP64bit(false), UseOddSPReg(true), + IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), + HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), + HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), + InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), + HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), + HasMSA(false), UseTCCInDIV(false), HasEVA(false), TM(TM), + TargetTriple(TT), TSInfo(), InstrInfo( MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))), FrameLowering(MipsFrameLowering::create(*this)), @@ -142,8 +142,7 @@ CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { MipsSubtarget & MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM) { - std::string CPUName = - MIPS_MC::selectMipsCPU(TargetTuple(TM.getTargetTriple()), CPU); + std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU); // Parse features string. ParseSubtargetFeatures(CPUName, FS); diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index d68389e2486..1c77745d130 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -48,8 +48,7 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle) { std::string Ret = ""; - MipsABIInfo ABI = - MipsABIInfo::computeTargetABI(TargetTuple(TT), CPU, Options.MCOptions); + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); // There are both little and big endian mips. if (isLittle) @@ -91,8 +90,7 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, CPU, FS, Options, RM, CM, OL), isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()), - ABI(MipsABIInfo::computeTargetABI(TargetTuple(TT), CPU, - Options.MCOptions)), + ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this), NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", isLittle, *this), diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp index 2eebf71ee2a..ef36c13b49f 100644 --- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp +++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #include "NVPTXMCAsmInfo.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" #include "llvm/Support/CommandLine.h" using namespace llvm; @@ -25,8 +25,8 @@ static cl::opt<bool> CompileForDebugging("debug-compile", void NVPTXMCAsmInfo::anchor() {} -NVPTXMCAsmInfo::NVPTXMCAsmInfo(const TargetTuple &TT) { - if (TT.getArch() == TargetTuple::nvptx64) { +NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Triple &TheTriple) { + if (TheTriple.getArch() == Triple::nvptx64) { PointerSize = CalleeSaveStackSlotSize = 8; } diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h index cf49c99e2e8..9ac3c8850f7 100644 --- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h +++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h @@ -18,13 +18,13 @@ namespace llvm { class Target; -class TargetTuple; +class Triple; class NVPTXMCAsmInfo : public MCAsmInfo { virtual void anchor(); public: - explicit NVPTXMCAsmInfo(const TargetTuple &TT); + explicit NVPTXMCAsmInfo(const Triple &TheTriple); }; } // namespace llvm diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp index fc74a86f903..ad7302037ca 100644 --- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp +++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp @@ -37,7 +37,7 @@ static MCInstrInfo *createNVPTXMCInstrInfo() { return X; } -static MCRegisterInfo *createNVPTXMCRegisterInfo(const TargetTuple &TT) { +static MCRegisterInfo *createNVPTXMCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); // PTX does not have a return address register. InitNVPTXMCRegisterInfo(X, 0); @@ -45,11 +45,11 @@ static MCRegisterInfo *createNVPTXMCRegisterInfo(const TargetTuple &TT) { } static MCSubtargetInfo * -createNVPTXMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS) { +createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createNVPTXMCSubtargetInfoImpl(TT, CPU, FS); } -static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const TargetTuple &TT, +static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -61,7 +61,7 @@ static MCCodeGenInfo *createNVPTXMCCodeGenInfo(const TargetTuple &TT, return X; } -static MCInstPrinter *createNVPTXMCInstPrinter(const TargetTuple &T, +static MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp index efc03c3e145..bd2509a3c8c 100644 --- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp @@ -46,9 +46,8 @@ NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU, NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const NVPTXTargetMachine &TM) - : NVPTXGenSubtargetInfo(TargetTuple(TT), CPU, FS), PTXVersion(0), - SmVersion(20), TM(TM), InstrInfo(), - TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), TSInfo(), + : NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM), + InstrInfo(), TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), FrameLowering() {} bool NVPTXSubtarget::hasImageHandles() const { diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index 4c90b211f5f..1ad3d07831a 100644 --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -295,10 +295,10 @@ public: const MCTargetOptions &Options) : MCTargetAsmParser(Options), STI(STI), MII(MII) { // Check for 64-bit vs. 32-bit pointer mode. - const TargetTuple &TT = STI.getTargetTuple(); - IsPPC64 = (TT.getArch() == TargetTuple::ppc64 || - TT.getArch() == TargetTuple::ppc64le); - IsDarwin = TT.isMacOSX(); + Triple TheTriple(STI.getTargetTriple()); + IsPPC64 = (TheTriple.getArch() == Triple::ppc64 || + TheTriple.getArch() == Triple::ppc64le); + IsDarwin = TheTriple.isMacOSX(); // Initialize the set of available features. setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp index 5dab79cda71..b6dd595ffb0 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -230,11 +230,11 @@ namespace { MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU) { + const Triple &TT, StringRef CPU) { if (TT.isOSDarwin()) return new DarwinPPCAsmBackend(T); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); - bool IsLittleEndian = TT.getArch() == TargetTuple::ppc64le; + bool IsLittleEndian = TT.getArch() == Triple::ppc64le; return new ELFPPCAsmBackend(T, IsLittleEndian, OSABI); } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp index dc434bc9b93..d8fab5b7c01 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp @@ -12,13 +12,13 @@ //===----------------------------------------------------------------------===// #include "PPCMCAsmInfo.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" using namespace llvm; void PPCMCAsmInfoDarwin::anchor() { } -PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const TargetTuple &TT) { +PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const Triple& T) { if (is64Bit) { PointerSize = CalleeSaveStackSlotSize = 8; } @@ -36,7 +36,7 @@ PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const TargetTuple &TT) { // The installed assembler for OSX < 10.6 lacks some directives. // FIXME: this should really be a check on the assembler characteristics // rather than OS version - if (TT.isMacOSX() && TT.isMacOSXVersionLT(10, 6)) + if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6)) HasWeakDefCanBeHiddenDirective = false; UseIntegratedAssembler = true; @@ -44,7 +44,7 @@ PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const TargetTuple &TT) { void PPCELFMCAsmInfo::anchor() { } -PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const TargetTuple &TT) { +PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const Triple& T) { // FIXME: This is not always needed. For example, it is not needed in the // v2 abi. NeedsLocalForSize = true; @@ -52,7 +52,7 @@ PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const TargetTuple &TT) { if (is64Bit) { PointerSize = CalleeSaveStackSlotSize = 8; } - IsLittleEndian = TT.getArch() == TargetTuple::ppc64le; + IsLittleEndian = T.getArch() == Triple::ppc64le; // ".comm align is in bytes but .align is pow-2." AlignmentIsInBytes = false; diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h index 958b5a6b4b7..e252ac944d4 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h @@ -18,20 +18,20 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class TargetTuple; +class Triple; class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin { virtual void anchor(); public: - explicit PPCMCAsmInfoDarwin(bool is64Bit, const TargetTuple &); + explicit PPCMCAsmInfoDarwin(bool is64Bit, const Triple &); }; class PPCELFMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit PPCELFMCAsmInfo(bool is64Bit, const TargetTuple &); + explicit PPCELFMCAsmInfo(bool is64Bit, const Triple &); }; } // namespace llvm diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 16dbd2be959..b7291561c75 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -309,9 +309,8 @@ unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, // Return the thread-pointer register's encoding. Fixups.push_back(MCFixup::create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_nofixup)); - const TargetTuple &TT = STI.getTargetTuple(); - bool isPPC64 = TT.getArch() == TargetTuple::ppc64 || - TT.getArch() == TargetTuple::ppc64le; + const Triple &TT = STI.getTargetTriple(); + bool isPPC64 = TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le; return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2); } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp index f6033df1bd5..30f232a9a91 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -51,9 +51,9 @@ static MCInstrInfo *createPPCMCInstrInfo() { return X; } -static MCRegisterInfo *createPPCMCRegisterInfo(const TargetTuple &TT) { - bool isPPC64 = (TT.getArch() == TargetTuple::ppc64 || - TT.getArch() == TargetTuple::ppc64le); +static MCRegisterInfo *createPPCMCRegisterInfo(const Triple &TT) { + bool isPPC64 = + (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le); unsigned Flavour = isPPC64 ? 0 : 1; unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; @@ -62,21 +62,21 @@ static MCRegisterInfo *createPPCMCRegisterInfo(const TargetTuple &TT) { return X; } -static MCSubtargetInfo *createPPCMCSubtargetInfo(const TargetTuple &TT, +static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createPPCMCSubtargetInfoImpl(TT, CPU, FS); } static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, - const TargetTuple &TT) { - bool isPPC64 = (TT.getArch() == TargetTuple::ppc64 || - TT.getArch() == TargetTuple::ppc64le); + const Triple &TheTriple) { + bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 || + TheTriple.getArch() == Triple::ppc64le); MCAsmInfo *MAI; - if (TT.isOSDarwin()) - MAI = new PPCMCAsmInfoDarwin(isPPC64, TT); + if (TheTriple.isOSDarwin()) + MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple); else - MAI = new PPCELFMCAsmInfo(isPPC64, TT); + MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple); // Initial state of the frame pointer is R1. unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1; @@ -87,8 +87,7 @@ static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createPPCMCCodeGenInfo(const TargetTuple &TT, - Reloc::Model RM, +static MCCodeGenInfo *createPPCMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { MCCodeGenInfo *X = new MCCodeGenInfo(); @@ -100,8 +99,8 @@ static MCCodeGenInfo *createPPCMCCodeGenInfo(const TargetTuple &TT, RM = Reloc::Static; } if (CM == CodeModel::Default) { - if (!TT.isOSDarwin() && (TT.getArch() == TargetTuple::ppc64 || - TT.getArch() == TargetTuple::ppc64le)) + if (!TT.isOSDarwin() && + (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le)) CM = CodeModel::Medium; } X->initMCCodeGenInfo(RM, CM, OL); @@ -226,18 +225,18 @@ static MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S, static MCTargetStreamer * createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { - const TargetTuple &TT = STI.getTargetTuple(); + const Triple &TT = STI.getTargetTriple(); if (TT.isOSBinFormatELF()) return new PPCTargetELFStreamer(S); return new PPCTargetMachOStreamer(S); } -static MCInstPrinter *createPPCMCInstPrinter(const TargetTuple &TT, +static MCInstPrinter *createPPCMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) { - return new PPCInstPrinter(MAI, MII, MRI, TT.isOSDarwin()); + return new PPCInstPrinter(MAI, MII, MRI, T.isOSDarwin()); } extern "C" void LLVMInitializePowerPCTargetMC() { diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h index 7792ae62e56..77fe4588228 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h @@ -29,7 +29,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; class Target; -class TargetTuple; +class Triple; class StringRef; class raw_pwrite_stream; class raw_ostream; @@ -43,7 +43,7 @@ MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); /// Construct an PPC ELF object writer. MCObjectWriter *createPPCELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp index 6ab15423e45..58daccae90f 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -49,7 +49,7 @@ PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const PPCTargetMachine &TM) - : PPCGenSubtargetInfo(TargetTuple(TT), CPU, FS), TargetTriple(TT), + : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), IsPPC64(TargetTriple.getArch() == Triple::ppc64 || TargetTriple.getArch() == Triple::ppc64le), TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 9a45a720574..6f13993fd01 100644 --- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -77,7 +77,7 @@ class SparcAsmParser : public MCTargetAsmParser { bool parseDirectiveWord(unsigned Size, SMLoc L); bool is64Bit() const { - return STI.getTargetTuple().getArch() == TargetTuple::sparcv9; + return STI.getTargetTriple().getArch() == Triple::sparcv9; } void expandSET(MCInst &Inst, SMLoc IDLoc, diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp index ebcc12042e9..d1d7aaa07ea 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -267,11 +267,10 @@ namespace { }; class ELFSparcAsmBackend : public SparcAsmBackend { - TargetTuple::OSType OSType; - + Triple::OSType OSType; public: - ELFSparcAsmBackend(const Target &T, TargetTuple::OSType OSType) - : SparcAsmBackend(T), OSType(OSType) {} + ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) : + SparcAsmBackend(T), OSType(OSType) { } void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, uint64_t Value, bool IsPCRel) const override { @@ -300,7 +299,6 @@ namespace { MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { return new ELFSparcAsmBackend(T, TT.getOS()); } diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp index 80233c8ab14..280c6d7937b 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp @@ -13,16 +13,16 @@ #include "SparcMCAsmInfo.h" #include "SparcMCExpr.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" #include "llvm/MC/MCStreamer.h" using namespace llvm; void SparcELFMCAsmInfo::anchor() {} -SparcELFMCAsmInfo::SparcELFMCAsmInfo(const TargetTuple &TT) { - bool isV9 = (TT.getArch() == TargetTuple::sparcv9); - IsLittleEndian = (TT.getArch() == TargetTuple::sparcel); +SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Triple &TheTriple) { + bool isV9 = (TheTriple.getArch() == Triple::sparcv9); + IsLittleEndian = (TheTriple.getArch() == Triple::sparcel); if (isV9) { PointerSize = CalleeSaveStackSlotSize = 8; diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h index 29db112fe52..ad441227600 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h @@ -17,13 +17,13 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class TargetTuple; +class Triple; class SparcELFMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit SparcELFMCAsmInfo(const TargetTuple &TT); + explicit SparcELFMCAsmInfo(const Triple &TheTriple); const MCExpr* getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding, MCStreamer &Streamer) const override; diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index 79c91c48e69..9113e4a46b9 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -34,7 +34,7 @@ using namespace llvm; #include "SparcGenRegisterInfo.inc" static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, - const TargetTuple &TT) { + const Triple &TT) { MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); @@ -43,7 +43,7 @@ static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, } static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, - const TargetTuple &TT) { + const Triple &TT) { MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047); @@ -57,16 +57,16 @@ static MCInstrInfo *createSparcMCInstrInfo() { return X; } -static MCRegisterInfo *createSparcMCRegisterInfo(const TargetTuple &TT) { +static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); InitSparcMCRegisterInfo(X, SP::O7); return X; } static MCSubtargetInfo * -createSparcMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS) { +createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { if (CPU.empty()) - CPU = (TT.getArch() == TargetTuple::sparcv9) ? "v9" : "v8"; + CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8"; return createSparcMCSubtargetInfoImpl(TT, CPU, FS); } @@ -81,7 +81,7 @@ createSparcMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS) { // // All code models require that the text segment is smaller than 2GB. -static MCCodeGenInfo *createSparcMCCodeGenInfo(const TargetTuple &TT, +static MCCodeGenInfo *createSparcMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -99,7 +99,7 @@ static MCCodeGenInfo *createSparcMCCodeGenInfo(const TargetTuple &TT, return X; } -static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const TargetTuple &TT, +static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -133,7 +133,7 @@ static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S, return new SparcTargetAsmStreamer(S, OS); } -static MCInstPrinter *createSparcMCInstPrinter(const TargetTuple &TT, +static MCInstPrinter *createSparcMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h index dc979576c38..a9c9f15454e 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h @@ -25,7 +25,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; class Target; -class TargetTuple; +class Triple; class StringRef; class raw_pwrite_stream; class raw_ostream; @@ -38,7 +38,7 @@ MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx); MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, bool IsLIttleEndian, uint8_t OSABI); } // End llvm namespace diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/llvm/lib/Target/Sparc/SparcSubtarget.cpp index 7c05ea7b3a7..d701594d27a 100644 --- a/llvm/lib/Target/Sparc/SparcSubtarget.cpp +++ b/llvm/lib/Target/Sparc/SparcSubtarget.cpp @@ -52,7 +52,7 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, TargetMachine &TM, bool is64Bit) - : SparcGenSubtargetInfo(TargetTuple(TT), CPU, FS), Is64Bit(is64Bit), + : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), FrameLowering(*this) {} diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp index 5c39fd48083..57eebe19c04 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp @@ -111,8 +111,7 @@ bool SystemZMCAsmBackend::writeNopData(uint64_t Count, MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, - StringRef CPU) { + const Triple &TT, StringRef CPU) { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); return new SystemZMCAsmBackend(OSABI); } diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp index aa69eb1ef97..b17977d41be 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp @@ -13,7 +13,7 @@ using namespace llvm; -SystemZMCAsmInfo::SystemZMCAsmInfo(const TargetTuple &TT) { +SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) { PointerSize = 8; CalleeSaveStackSlotSize = 8; IsLittleEndian = false; diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h index 6047e75a34c..800f8923206 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h @@ -14,11 +14,11 @@ #include "llvm/Support/Compiler.h" namespace llvm { -class TargetTuple; +class Triple; class SystemZMCAsmInfo : public MCAsmInfoELF { public: - explicit SystemZMCAsmInfo(const TargetTuple &TT); + explicit SystemZMCAsmInfo(const Triple &TT); }; } // end namespace llvm diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp index b84c5bc2188..5fefa315a4c 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -132,7 +132,7 @@ unsigned SystemZMC::getFirstReg(unsigned Reg) { } static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, - const TargetTuple &TT) { + const Triple &TT) { MCAsmInfo *MAI = new SystemZMCAsmInfo(TT); MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, @@ -148,19 +148,18 @@ static MCInstrInfo *createSystemZMCInstrInfo() { return X; } -static MCRegisterInfo *createSystemZMCRegisterInfo(const TargetTuple &TT) { +static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); InitSystemZMCRegisterInfo(X, SystemZ::R14D); return X; } -static MCSubtargetInfo *createSystemZMCSubtargetInfo(const TargetTuple &TT, - StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createSystemZMCSubtargetInfoImpl(TT, CPU, FS); } -static MCCodeGenInfo *createSystemZMCCodeGenInfo(const TargetTuple &TT, +static MCCodeGenInfo *createSystemZMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -208,7 +207,7 @@ static MCCodeGenInfo *createSystemZMCCodeGenInfo(const TargetTuple &TT, return X; } -static MCInstPrinter *createSystemZMCInstPrinter(const TargetTuple &T, +static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h index 80c863df951..0db48fe5a10 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -23,7 +23,7 @@ class MCRegisterInfo; class MCSubtargetInfo; class StringRef; class Target; -class TargetTuple; +class Triple; class raw_pwrite_stream; class raw_ostream; @@ -85,7 +85,7 @@ MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII, MCAsmBackend *createSystemZMCAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI); } // end namespace llvm diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp index 220cb5693d7..0b49fcdd8f7 100644 --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -35,7 +35,7 @@ SystemZSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) - : SystemZGenSubtargetInfo(TargetTuple(TT), CPU, FS), HasDistinctOps(false), + : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false), HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false), HasPopulationCount(false), HasFastSerialization(false), HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), diff --git a/llvm/lib/Target/TargetSubtargetInfo.cpp b/llvm/lib/Target/TargetSubtargetInfo.cpp index cb1fb6b8f34..6a61fcdf0f8 100644 --- a/llvm/lib/Target/TargetSubtargetInfo.cpp +++ b/llvm/lib/Target/TargetSubtargetInfo.cpp @@ -20,7 +20,7 @@ using namespace llvm; // TargetSubtargetInfo Class // TargetSubtargetInfo::TargetSubtargetInfo( - const TargetTuple &TT, StringRef CPU, StringRef FS, + const Triple &TT, StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp index a8cb8084843..2e353cbb9a2 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp @@ -1068,8 +1068,8 @@ unsigned X86AsmInstrumentation::GetFrameRegGeneric(const MCContext &Ctx, X86AsmInstrumentation * CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions, const MCContext &Ctx, const MCSubtargetInfo &STI) { - const TargetTuple &TT = STI.getTargetTuple(); - const bool hasCompilerRTSupport = TT.isOSLinux(); + Triple T(STI.getTargetTriple()); + const bool hasCompilerRTSupport = T.isOSLinux(); if (ClAsanInstrumentAssembly && hasCompilerRTSupport && MCOptions.SanitizeAddress) { if (STI.getFeatureBits()[X86::Mode32Bit] != 0) diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp index dc2b07c9016..629802f5dc5 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -771,36 +771,36 @@ public: MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, + const Triple &TheTriple, StringRef CPU) { - if (TT.isOSBinFormatMachO()) + if (TheTriple.isOSBinFormatMachO()) return new DarwinX86_32AsmBackend(T, MRI, CPU); - if (TT.isOSWindows() && !TT.isOSBinFormatELF()) + if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF()) return new WindowsX86AsmBackend(T, false, CPU); - uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); return new ELFX86_32AsmBackend(T, OSABI, CPU); } MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, + const Triple &TheTriple, StringRef CPU) { - if (TT.isOSBinFormatMachO()) { + if (TheTriple.isOSBinFormatMachO()) { MachO::CPUSubTypeX86 CS = - StringSwitch<MachO::CPUSubTypeX86>(TT.getArchName()) + StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName()) .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H) .Default(MachO::CPU_SUBTYPE_X86_64_ALL); return new DarwinX86_64AsmBackend(T, MRI, CPU, CS); } - if (TT.isOSWindows() && !TT.isOSBinFormatELF()) + if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF()) return new WindowsX86AsmBackend(T, true, CPU); - uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); - if (TT.getEnvironment() == TargetTuple::GNUX32) + if (TheTriple.getEnvironment() == Triple::GNUX32) return new ELFX86_X32AsmBackend(T, OSABI, CPU); return new ELFX86_64AsmBackend(T, OSABI, CPU); } diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp index 2208d9c2bff..fc0b0f89e23 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #include "X86MCAsmInfo.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCSectionELF.h" @@ -41,8 +41,8 @@ MarkedJTDataRegions("mark-data-regions", cl::init(false), void X86MCAsmInfoDarwin::anchor() { } -X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const TargetTuple &TT) { - bool is64Bit = TT.getArch() == TargetTuple::x86_64; +X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &T) { + bool is64Bit = T.getArch() == Triple::x86_64; if (is64Bit) PointerSize = CalleeSaveStackSlotSize = 8; @@ -69,7 +69,7 @@ X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const TargetTuple &TT) { // old assembler lacks some directives // FIXME: this should really be a check on the assembler characteristics // rather than OS version - if (TT.isMacOSX() && TT.isMacOSXVersionLT(10, 6)) + if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6)) HasWeakDefCanBeHiddenDirective = false; // Assume ld64 is new enough that the abs-ified FDE relocs may be used @@ -80,14 +80,15 @@ X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const TargetTuple &TT) { UseIntegratedAssembler = true; } -X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const TargetTuple &TT) - : X86MCAsmInfoDarwin(TT) {} +X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const Triple &Triple) + : X86MCAsmInfoDarwin(Triple) { +} void X86ELFMCAsmInfo::anchor() { } -X86ELFMCAsmInfo::X86ELFMCAsmInfo(const TargetTuple &TT) { - bool is64Bit = TT.getArch() == TargetTuple::x86_64; - bool isX32 = TT.getEnvironment() == TargetTuple::GNUX32; +X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) { + bool is64Bit = T.getArch() == Triple::x86_64; + bool isX32 = T.getEnvironment() == Triple::GNUX32; // For ELF, x86-64 pointer size depends on the ABI. // For x86-64 without the x32 ABI, pointer size is 8. For x86 and for x86-64 @@ -125,8 +126,8 @@ X86_64MCAsmInfoDarwin::getExprForPersonalitySymbol(const MCSymbol *Sym, void X86MCAsmInfoMicrosoft::anchor() { } -X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const TargetTuple &TT) { - if (TT.getArch() == TargetTuple::x86_64) { +X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const Triple &Triple) { + if (Triple.getArch() == Triple::x86_64) { PrivateGlobalPrefix = ".L"; PrivateLabelPrefix = ".L"; PointerSize = 8; @@ -151,9 +152,9 @@ X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const TargetTuple &TT) { void X86MCAsmInfoGNUCOFF::anchor() { } -X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const TargetTuple &TT) { - assert(TT.isOSWindows() && "Windows is the only supported COFF target"); - if (TT.getArch() == TargetTuple::x86_64) { +X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const Triple &Triple) { + assert(Triple.isOSWindows() && "Windows is the only supported COFF target"); + if (Triple.getArch() == Triple::x86_64) { PrivateGlobalPrefix = ".L"; PrivateLabelPrefix = ".L"; PointerSize = 8; diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h index 8bb860e2cc0..30d5c802d1e 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h @@ -20,17 +20,17 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class TargetTuple; +class Triple; class X86MCAsmInfoDarwin : public MCAsmInfoDarwin { virtual void anchor(); public: - explicit X86MCAsmInfoDarwin(const TargetTuple &TT); + explicit X86MCAsmInfoDarwin(const Triple &Triple); }; struct X86_64MCAsmInfoDarwin : public X86MCAsmInfoDarwin { - explicit X86_64MCAsmInfoDarwin(const TargetTuple &TT); + explicit X86_64MCAsmInfoDarwin(const Triple &Triple); const MCExpr * getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding, MCStreamer &Streamer) const override; @@ -40,21 +40,21 @@ class X86ELFMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit X86ELFMCAsmInfo(const TargetTuple &TT); + explicit X86ELFMCAsmInfo(const Triple &Triple); }; class X86MCAsmInfoMicrosoft : public MCAsmInfoMicrosoft { void anchor() override; public: - explicit X86MCAsmInfoMicrosoft(const TargetTuple &TT); + explicit X86MCAsmInfoMicrosoft(const Triple &Triple); }; class X86MCAsmInfoGNUCOFF : public MCAsmInfoGNUCOFF { void anchor() override; public: - explicit X86MCAsmInfoGNUCOFF(const TargetTuple &TT); + explicit X86MCAsmInfoGNUCOFF(const Triple &Triple); }; } // namespace llvm diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp index 9ece4ee0f35..7a453fea23b 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -15,7 +15,7 @@ #include "InstPrinter/X86ATTInstPrinter.h" #include "InstPrinter/X86IntelInstPrinter.h" #include "X86MCAsmInfo.h" -#include "llvm/ADT/TargetTuple.h" +#include "llvm/ADT/Triple.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" @@ -42,11 +42,11 @@ using namespace llvm; #define GET_SUBTARGETINFO_MC_DESC #include "X86GenSubtargetInfo.inc" -std::string X86_MC::ParseX86TargetTuple(const TargetTuple &TT) { +std::string X86_MC::ParseX86Triple(const Triple &TT) { std::string FS; - if (TT.getArch() == TargetTuple::x86_64) + if (TT.getArch() == Triple::x86_64) FS = "+64bit-mode,-32bit-mode,-16bit-mode"; - else if (TT.getEnvironment() != TargetTuple::CODE16) + else if (TT.getEnvironment() != Triple::CODE16) FS = "-64bit-mode,+32bit-mode,-16bit-mode"; else FS = "-64bit-mode,-32bit-mode,+16bit-mode"; @@ -54,8 +54,8 @@ std::string X86_MC::ParseX86TargetTuple(const TargetTuple &TT) { return FS; } -unsigned X86_MC::getDwarfRegFlavour(const TargetTuple &TT, bool isEH) { - if (TT.getArch() == TargetTuple::x86_64) +unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { + if (TT.getArch() == Triple::x86_64) return DWARFFlavour::X86_64; if (TT.isOSDarwin()) @@ -74,9 +74,9 @@ void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { } } -MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const TargetTuple &TT, +MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { - std::string ArchFS = X86_MC::ParseX86TargetTuple(TT); + std::string ArchFS = X86_MC::ParseX86Triple(TT); if (!FS.empty()) { if (!ArchFS.empty()) ArchFS = (Twine(ArchFS) + "," + FS).str(); @@ -97,8 +97,8 @@ static MCInstrInfo *createX86MCInstrInfo() { return X; } -static MCRegisterInfo *createX86MCRegisterInfo(const TargetTuple &TT) { - unsigned RA = (TT.getArch() == TargetTuple::x86_64) +static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { + unsigned RA = (TT.getArch() == Triple::x86_64) ? X86::RIP // Should have dwarf #16. : X86::EIP; // Should have dwarf #8. @@ -110,26 +110,27 @@ static MCRegisterInfo *createX86MCRegisterInfo(const TargetTuple &TT) { } static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, - const TargetTuple &TT) { - bool is64Bit = TT.getArch() == TargetTuple::x86_64; + const Triple &TheTriple) { + bool is64Bit = TheTriple.getArch() == Triple::x86_64; MCAsmInfo *MAI; - if (TT.isOSBinFormatMachO()) { + if (TheTriple.isOSBinFormatMachO()) { if (is64Bit) - MAI = new X86_64MCAsmInfoDarwin(TT); + MAI = new X86_64MCAsmInfoDarwin(TheTriple); else - MAI = new X86MCAsmInfoDarwin(TT); - } else if (TT.isOSBinFormatELF()) { + MAI = new X86MCAsmInfoDarwin(TheTriple); + } else if (TheTriple.isOSBinFormatELF()) { // Force the use of an ELF container. - MAI = new X86ELFMCAsmInfo(TT); - } else if (TT.isWindowsMSVCEnvironment() || - TT.isWindowsCoreCLREnvironment()) { - MAI = new X86MCAsmInfoMicrosoft(TT); - } else if (TT.isOSCygMing() || TT.isWindowsItaniumEnvironment()) { - MAI = new X86MCAsmInfoGNUCOFF(TT); + MAI = new X86ELFMCAsmInfo(TheTriple); + } else if (TheTriple.isWindowsMSVCEnvironment() || + TheTriple.isWindowsCoreCLREnvironment()) { + MAI = new X86MCAsmInfoMicrosoft(TheTriple); + } else if (TheTriple.isOSCygMing() || + TheTriple.isWindowsItaniumEnvironment()) { + MAI = new X86MCAsmInfoGNUCOFF(TheTriple); } else { // The default is ELF. - MAI = new X86ELFMCAsmInfo(TT); + MAI = new X86ELFMCAsmInfo(TheTriple); } // Initialize initial frame state. @@ -151,13 +152,12 @@ static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createX86MCCodeGenInfo(const TargetTuple &TT, - Reloc::Model RM, +static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { MCCodeGenInfo *X = new MCCodeGenInfo(); - bool is64Bit = TT.getArch() == TargetTuple::x86_64; + bool is64Bit = TT.getArch() == Triple::x86_64; if (RM == Reloc::Default) { // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. @@ -201,7 +201,7 @@ static MCCodeGenInfo *createX86MCCodeGenInfo(const TargetTuple &TT, return X; } -static MCInstPrinter *createX86MCInstPrinter(const TargetTuple &TT, +static MCInstPrinter *createX86MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, @@ -213,14 +213,14 @@ static MCInstPrinter *createX86MCInstPrinter(const TargetTuple &TT, return nullptr; } -static MCRelocationInfo *createX86MCRelocationInfo(const TargetTuple &TT, +static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, MCContext &Ctx) { - if (TT.isOSBinFormatMachO() && TT.getArch() == TargetTuple::x86_64) + if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64) return createX86_64MachORelocationInfo(Ctx); - else if (TT.isOSBinFormatELF()) + else if (TheTriple.isOSBinFormatELF()) return createX86_64ELFRelocationInfo(Ctx); // Default to the stock relocation info. - return llvm::createMCRelocationInfo(TT, Ctx); + return llvm::createMCRelocationInfo(TheTriple, Ctx); } static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h index 18a6e263bf5..6221baba179 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h @@ -28,7 +28,7 @@ class MCSubtargetInfo; class MCRelocationInfo; class MCStreamer; class Target; -class TargetTuple; +class Triple; class StringRef; class raw_ostream; class raw_pwrite_stream; @@ -52,15 +52,15 @@ namespace N86 { } namespace X86_MC { -std::string ParseX86TargetTuple(const TargetTuple &TT); +std::string ParseX86Triple(const Triple &TT); -unsigned getDwarfRegFlavour(const TargetTuple &TT, bool isEH); +unsigned getDwarfRegFlavour(const Triple &TT, bool isEH); void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc. /// do not need to go through TargetRegistry. -MCSubtargetInfo *createX86MCSubtargetInfo(const TargetTuple &TT, StringRef CPU, +MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS); } @@ -69,9 +69,9 @@ MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); /// Construct an X86 Windows COFF machine code streamer which will generate /// PE/COFF format object files. diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index 57f4c99f2d8..7b04e81c483 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -50,8 +50,8 @@ EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), X86RegisterInfo::X86RegisterInfo(const Triple &TT) : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), - X86_MC::getDwarfRegFlavour(TargetTuple(TT), false), - X86_MC::getDwarfRegFlavour(TargetTuple(TT), true), + X86_MC::getDwarfRegFlavour(TT, false), + X86_MC::getDwarfRegFlavour(TT, true), (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { X86_MC::InitLLVM2SEHRegisterMapping(this); diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp index 111e12baaac..5b53ca93399 100644 --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -290,7 +290,7 @@ X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU, X86Subtarget::X86Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const X86TargetMachine &TM, unsigned StackAlignOverride) - : X86GenSubtargetInfo(TargetTuple(TT), CPU, FS), X86ProcFamily(Others), + : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others), PICStyle(PICStyles::None), TargetTriple(TT), StackAlignOverride(StackAlignOverride), In64BitMode(TargetTriple.getArch() == Triple::x86_64), diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp index 1d25ff3a0ef..3178a4edbb3 100644 --- a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp @@ -12,7 +12,7 @@ using namespace llvm; void XCoreMCAsmInfo::anchor() { } -XCoreMCAsmInfo::XCoreMCAsmInfo(const TargetTuple &TT) { +XCoreMCAsmInfo::XCoreMCAsmInfo(const Triple &TT) { SupportsDebugInformation = true; Data16bitsDirective = "\t.short\t"; Data32bitsDirective = "\t.long\t"; diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h index 26adae96174..39581e424e8 100644 --- a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h @@ -17,13 +17,13 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class TargetTuple; +class Triple; class XCoreMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit XCoreMCAsmInfo(const TargetTuple &TT); + explicit XCoreMCAsmInfo(const Triple &TT); }; } // namespace llvm diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp index 05c2c6278c3..b4085835f28 100644 --- a/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -40,19 +40,19 @@ static MCInstrInfo *createXCoreMCInstrInfo() { return X; } -static MCRegisterInfo *createXCoreMCRegisterInfo(const TargetTuple &TT) { +static MCRegisterInfo *createXCoreMCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); InitXCoreMCRegisterInfo(X, XCore::LR); return X; } static MCSubtargetInfo * -createXCoreMCSubtargetInfo(const TargetTuple &TT, StringRef CPU, StringRef FS) { +createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createXCoreMCSubtargetInfoImpl(TT, CPU, FS); } static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, - const TargetTuple &TT) { + const Triple &TT) { MCAsmInfo *MAI = new XCoreMCAsmInfo(TT); // Initial state of the frame pointer is SP. @@ -62,7 +62,7 @@ static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createXCoreMCCodeGenInfo(const TargetTuple &TT, +static MCCodeGenInfo *createXCoreMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -80,7 +80,7 @@ static MCCodeGenInfo *createXCoreMCCodeGenInfo(const TargetTuple &TT, return X; } -static MCInstPrinter *createXCoreMCInstPrinter(const TargetTuple &T, +static MCInstPrinter *createXCoreMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, diff --git a/llvm/lib/Target/XCore/XCoreSubtarget.cpp b/llvm/lib/Target/XCore/XCoreSubtarget.cpp index 759d1f45bb4..99ad2c88504 100644 --- a/llvm/lib/Target/XCore/XCoreSubtarget.cpp +++ b/llvm/lib/Target/XCore/XCoreSubtarget.cpp @@ -27,5 +27,5 @@ void XCoreSubtarget::anchor() { } XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) - : XCoreGenSubtargetInfo(TargetTuple(TT), CPU, FS), InstrInfo(), - FrameLowering(*this), TLInfo(TM, *this), TSInfo() {} + : XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this), + TLInfo(TM, *this), TSInfo() {} |
