1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
index 18a6e263bf5..6221baba179 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
@@ -28,7 +28,7 @@ class MCSubtargetInfo;
 class MCRelocationInfo;
 class MCStreamer;
 class Target;
-class TargetTuple;
+class Triple;
 class StringRef;
 class raw_ostream;
 class raw_pwrite_stream;
@@ -52,15 +52,15 @@ namespace N86 {
 }
 
 namespace X86_MC {
-std::string ParseX86TargetTuple(const TargetTuple &TT);
+std::string ParseX86Triple(const Triple &TT);
 
-unsigned getDwarfRegFlavour(const TargetTuple &TT, bool isEH);
+unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
 
 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
 
 /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
 /// do not need to go through TargetRegistry.
-MCSubtargetInfo *createX86MCSubtargetInfo(const TargetTuple &TT, StringRef CPU,
+MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
                                           StringRef FS);
 }
 
@@ -69,9 +69,9 @@ MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
                                       MCContext &Ctx);
 
 MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                     const TargetTuple &TT, StringRef CPU);
+                                     const Triple &TT, StringRef CPU);
 MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                     const TargetTuple &TT, StringRef CPU);
+                                     const Triple &TT, StringRef CPU);
 
 /// Construct an X86 Windows COFF machine code streamer which will generate
 /// PE/COFF format object files.