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authorChris Lattner <sabre@nondot.org>2007-12-30 21:01:27 +0000
committerChris Lattner <sabre@nondot.org>2007-12-30 21:01:27 +0000
commit49bd29daa026b997f900f874b4c6b33bfc4de3e4 (patch)
tree4bf12b1d87d89bb3be2d374fd04c418c6c5db709 /llvm/lib
parent0dad74d25265095c604a7c4593d0021ce892f7b4 (diff)
downloadbcm5719-llvm-49bd29daa026b997f900f874b4c6b33bfc4de3e4.tar.gz
bcm5719-llvm-49bd29daa026b997f900f874b4c6b33bfc4de3e4.zip
Simplify and clean up some machine operand/instr printing/dumping stuff.
llvm-svn: 45456
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/MachineInstr.cpp18
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index e8f692e15f8..49ceab70415 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -267,15 +267,16 @@ void MachineInstr::dump() const {
cerr << " " << *this;
}
-static inline void OutputReg(std::ostream &os, unsigned RegNo,
- const MRegisterInfo *MRI = 0) {
- if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
+static void OutputReg(std::ostream &os, unsigned RegNo,
+ const MRegisterInfo *MRI = 0) {
+ if (MRegisterInfo::isPhysicalRegister(RegNo)) {
if (MRI)
os << "%" << MRI->get(RegNo).Name;
else
- os << "%mreg(" << RegNo << ")";
- } else
+ os << "%mreg" << RegNo;
+ } else {
os << "%reg" << RegNo;
+ }
}
static void print(const MachineOperand &MO, std::ostream &OS,
@@ -287,6 +288,7 @@ static void print(const MachineOperand &MO, std::ostream &OS,
switch (MO.getType()) {
case MachineOperand::MO_Register:
OutputReg(OS, MO.getReg(), MRI);
+ if (MO.isDef()) OS << "<d>";
break;
case MachineOperand::MO_Immediate:
OS << MO.getImm();
@@ -384,11 +386,8 @@ void MachineInstr::print(std::ostream &os) const {
// and such.
os << getInstrDescriptor()->Name;
- for (unsigned i = 0, N = getNumOperands(); i < N; i++) {
+ for (unsigned i = 0, N = getNumOperands(); i < N; i++)
os << "\t" << getOperand(i);
- if (getOperand(i).isRegister() && getOperand(i).isDef())
- os << "<d>";
- }
os << "\n";
}
@@ -397,6 +396,7 @@ void MachineOperand::print(std::ostream &OS) const {
switch (getType()) {
case MO_Register:
OutputReg(OS, getReg());
+ if (isDef()) OS << "<d>";
break;
case MO_Immediate:
OS << getImm();
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