diff options
author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-04-04 14:40:53 +0000 |
---|---|---|
committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-04-04 14:40:53 +0000 |
commit | 448222d8bad122e857df2356ae15b2a5c12b2590 (patch) | |
tree | a90a3477054597b35a0a78e36f4c96cba0fdd14f /llvm/lib | |
parent | 80af9c081a667812f8035e4a87a62a07343385c2 (diff) | |
download | bcm5719-llvm-448222d8bad122e857df2356ae15b2a5c12b2590.tar.gz bcm5719-llvm-448222d8bad122e857df2356ae15b2a5c12b2590.zip |
Strip trailing whitespace
llvm-svn: 299438
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index e3fee6fbb63..22afa6995cc 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -29328,14 +29328,14 @@ static SDValue combineBasicSADPattern(SDNode *Extract, SelectionDAG &DAG, SDValue Root = matchBinOpReduction(Extract, ISD::ADD); // The operand is expected to be zero extended from i8 - // (verified in detectZextAbsDiff). - // In order to convert to i64 and above, additional any/zero/sign + // (verified in detectZextAbsDiff). + // In order to convert to i64 and above, additional any/zero/sign // extend is expected. // The zero extend from 32 bit has no mathematical effect on the result. - // Also the sign extend is basically zero extend + // Also the sign extend is basically zero extend // (extends the sign bit which is zero). // So it is correct to skip the sign/zero extend instruction. - if (Root && (Root.getOpcode() == ISD::SIGN_EXTEND || + if (Root && (Root.getOpcode() == ISD::SIGN_EXTEND || Root.getOpcode() == ISD::ZERO_EXTEND || Root.getOpcode() == ISD::ANY_EXTEND)) Root = Root.getOperand(0); |