diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index e3fee6fbb63..22afa6995cc 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -29328,14 +29328,14 @@ static SDValue combineBasicSADPattern(SDNode *Extract, SelectionDAG &DAG, SDValue Root = matchBinOpReduction(Extract, ISD::ADD); // The operand is expected to be zero extended from i8 - // (verified in detectZextAbsDiff). - // In order to convert to i64 and above, additional any/zero/sign + // (verified in detectZextAbsDiff). + // In order to convert to i64 and above, additional any/zero/sign // extend is expected. // The zero extend from 32 bit has no mathematical effect on the result. - // Also the sign extend is basically zero extend + // Also the sign extend is basically zero extend // (extends the sign bit which is zero). // So it is correct to skip the sign/zero extend instruction. - if (Root && (Root.getOpcode() == ISD::SIGN_EXTEND || + if (Root && (Root.getOpcode() == ISD::SIGN_EXTEND || Root.getOpcode() == ISD::ZERO_EXTEND || Root.getOpcode() == ISD::ANY_EXTEND)) Root = Root.getOperand(0); |
